Product category:
Design and Development Software
News Release from: Aldec | Subject: Active-HDL 6.2
Edited by the Electronicstalk Editorial
Team on 08 January 2004
More speed and features for HDL
designers
In addition to a twofold performance increase over the previous version, Active-HDL 6.2 includes an improved advanced dataflow, library encryption, branch coverage and X-Trace.
In addition to a twofold performance increase over the previous version, Active-HDL 6.2 includes an improved advanced dataflow, library encryption, branch coverage and X-Trace The advancements in Active-HDL 6.2 provide industry-leading performance not only in verification times, but its new features simplify the design creation and debugging process for VHDL, Verilog and mixed language designs
This article was originally published on Electronicstalk on 1 Jul 2008 at 8.00am (UK)
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Aldec has increased the behavioural, gate-level and timing simulation performance with the release of Active-HDL 6.2.
Performance optimisations have yielded as much as a 2x improvement for VHDL, Verilog and mixed designs on all supported platforms.
"Active-HDL 6.2 offers designers a low cost robust Windows-based HDL design environment", stated Kathryn Bass, Product Marketing Manager for Aldec.
Further reading
New interface simplifies design verification
Co-simulation support for fixed-point in Simulink simplifies verification of hardware designs in Active-HDL.
Third party development support for FPGAs
Active-HDL Design Flow Manager supports the Cyclone III FPGA family and provides access to Altera's Quartus II software version 7.0 and third-party synthesis tools.
Verification environment moves up to Stratix III
Aldec has announced System Verification Environment (SVE) support for Altera Corporation's new high-end Stratix III FPGA device family.
"The 6.2 release not only provides increased simulation performance, but it also gives our customers a much more dynamic product as a result of the enhancements to our advanced dataflow and the additional code validation provided with branch coverage.
This release reaches a new level of performance and functionality for Aldec.
Our customers demand the most innovative HDL entry and verification technology and this is what we are committed to delivering".
The advanced dataflow window allows the designer to explore the connectivity of the simulated design and analyse the dataflow among instances, concurrent statements, signals, nets and registers.
Design objects are displayed in the diagram window and can be viewed in hierarchical or flattened modes.
Branch coverage has been added to Active-HDL 6.2 and gives the user additional assurance that the HDL code is correctly tested by the testbench.
In addition to line, unit and toggle coverage, this makes the code coverage program an invaluable tool for high reliability designs.
Active-HDL now includes the X-Trace command that creates a report with information about unknown values in the simulation model.
Each X-Trace report entry can be saved as a text or HTML file and includes simulation time and full hierarchical names of the signal that experienced an unknown value.
Active HDL 6.2 now supports encrypted libraries for protecting HDL code compiled in the design.
A workspace splitter that allows up to four windows in one integrated desktop frame, precompiled SystemC libraries, Matlab/Simulink, Celoxica interface and Asian language support are also part of the new release.
Active-HDL conforms to IEEE standards for VHDL and Verilog and provides a complete FPGA vendor independent solution.
Active-HDL 6.2, which is available today, includes multi-design workspace, HDL editor, state machine editor, block diagram and schematic editors, automatic testbench generation, simulation design profiler, signal agent, waveform viewer/editor, and a choice of VHDL, Verilog or mixed VHDL/Verilog/EDIF simulation.
All sales include one year of product maintenance.
US pricing for Active-HDL 6.2 begins at $5900 and is sold direct from Aldec.
A free evaluation copy of Active-HDL 6.2 is available from the Aldec website.
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