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Upgrades accelerate mixed-language simulation

An Aldec product story
Edited by the Electronicstalk editorial team Apr 22, 2004

Riviera 2004.04 features a mixed-design simulation performance increase of up to 2x over the previous version.

Riviera 2004.04 features a mixed-design simulation performance increase of up to 2x over the previous version.

In addition, new support for Verilog 2001 and a new assertions manager that supports both OVA and PSL will assist designers in verification of their complex ICs.

Aldec has increased the performance of Riviera 2004.04 over the previous release yielding as much as a 2x speed-up for mixed VHDL and Verilog designs.

This performance increase was achieved by optimising the communication between language compilers and additional optimisation of the VHDL and Verilog compilers individually.

Additional performance increases came from the new waveform database structure (.asdb), which has been completely implemented in Riviera 2004.04.

It now includes new debugging and graphical interface improvements to provide customers with one of the fastest operating system-independent RTL debugging environments available.

Riviera 2004.04 provides improved support for assertion-based verification and includes a new assertion viewer, templates and a language assistant.

The graphical assertion viewer helps designers easily identify and use the information by showing all assertions in the simulated model.

In addition, it provides statistics including the number of assertions that have failed in the current simulation, the number of passed assertions, and the last time a given assertion was violated.

Riviera 2004.04 also includes several new improvements to help the designer use assertions such as predefined templates and an assertion language assistant.

Complete OpenVera Assertions (OVA) and initial Property Specific Language (PSL) support is included with Riviera 2004.04.

Aldec has also implemented new constructs for Verilog 1364-2001.

New Verilog 2001 support includes such constructs as generate-loop, -case and -conditional statements as well as automatic (re-entrant) tasks/functions.

These constructs allow the designer to use a more robust coding style when describing their Verilog design.

The IEEE Verilog 1364-2001 standard includes Verilog 1995, 2001 and SystemVerilog, all are supported by Aldec.

"Riviera 2004.04 maintains Aldec's continued commitment to improving our technology while responding to the constant evolution in the industry with new design methodologies and techniques such as assertions and Verilog 2001", stated Eric Seabrook, Product Marketing Manager for Aldec, adding, "Riviera is considered one of the best verification tools Aldec has ever produced and will continue to evolve with the ever changing language requirements in EDA".

Riviera 2004.04 is available today based on a floating OS-independent license that supports Unix, Windows and Linux.

Pricing for Riviera 2004.04 begins at US $12,450 and is sold directly by Aldec in the USA and by authorised international distributors.

A free evaluation copy is available from the Aldec website.

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