Coverification speeds ARM development

The latest version of Riviera-IPT provides a seamless, high-speed coverification and debug environment for complex embedded software/hardware codevelopment using ARM processors.

The latest version of Riviera-IPT provides a seamless, high-speed coverification and debug environment for complex embedded software/hardware codevelopment using ARM processors.

Using Riviera-IPT's hardware accelerator with ARM allows engineers to run their designs at megahertz speed which is not possible using software models alone.

In contrast, while emulation provides similar speed, it is limited by the inability to debug the design on-the-fly and requires lengthy set-up.

Riviera-IPT provides the best of both as demand for better system-level verification solutions increases.

"Using Riviera-IPT for software/hardware coverification with ARM allows design teams to work in parallel much earlier in the design cycle to verify system-level functionality without all of the drawbacks normally associated with this process", stated Eric Seabrook, Product Marketing Manager for Aldec.

"Riviera-IPT combines the best in a HDL simulator, software debug, hardware acceleration and processor in a seamless environment", Seabrook added.

Riviera-IPT's Design Verification Manager (DVM) connects the HDL simulator, software debugger, acceleration board and the ARM processor from a single environment and provides the designer easy access to all logic states for analysis and debug.

Standard hardware debugging is provided via Riviera while the ARM processor uses the standard ARM debugging software.

Custom hardware is written in a HDL, synthesised, and downloaded into Aldec's acceleration board while software is written in C/C++ or an assembly language.

It is then compiled into the ARM processor and downloaded into system memory located on the ARM board.

Coverification can be executed using several types of testbenches including Verilog, VHDL, C/C++, SystemC or SystemVerilog and the results are collected and viewed in the Riviera-IPT environment.

The HDL simulator and ARM debugger both connect to Aldec's accelerator board and ARM's processor while the software and hardware modules run in the target environment.

All the information about the program state is viewed by the ARM debugger while the hardware state is seen via Aldec's HDL simulator.

All hardware modules can reside either on the accelerator board or in software.

In hardware, they are synthesised and implemented into the FPGA.

All peripherals are connected through the AMBA bus with the ARM processor and simulate together.

Riviera-IPT 2004.04 with ARM is available today based on a floating OS-independent licence that supports Unix, Windows and Linux.

Pricing starts at $90,000 for one year or the product can be leased for less than $10,000 per quarter.

It is sold directly by Aldec in the USA and authorised international distributors.

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