Affordable acceleration for RTL verification

Riviera-IPT Desktop brings Aldec's acceleration technology to the mainstream EDA market.

Riviera-IPT Desktop brings Aldec's acceleration technology to the mainstream EDA market.

This new version will offer an affordable option for RTL debugging and verification and a better solution to software simulation alone for design verification engineers.

Based on Aldec's popular Riviera-IPT Platform, which provides hardware acceleration for ASICs and large FPGAs, the Desktop version allows engineers to run and debug their RTL code from a local PC or workstation prior to system-level verification and at a much higher speed than with a typical software simulator alone.

Riviera-IPT Desktop's acceleration capabilities provide the design engineer with a simple turnkey solution to address the market segment that is still plagued with increasing design size and limited verification time.

Current acceleration and emulation solutions have not addressed the front-end verification process but instead concentrate on the back-end system-level verification process, or hardware prototyping, where there are typically fewer engineers.

Riviera-IPT Desktop allows more engineers to have access to this type of acceleration technology.

"Riviera-IPT Desktop is an affordable way for companies to accelerate the verification process from both ends".

"It provides acceleration to mainstream designers that may be priced out of the high-end solutions but are still looking for superior quality and performance", stated Eric Seabrook, Product Marketing Manager for Aldec.

"Most of the features from our original platform acceleration solution still exist in the desktop version, minus the items that are typically needed for ASIC verification and system prototyping", Seabrook added.

Riviera-IPT Desktop is a hardware acceleration solution based on Aldec's industry-proven mixed-language simulation technology.

The product includes Aldec's Design Verification Manager (DVM), simulator, and a hardware accelerator with capacity up to 12 million gates.

The Design Verification Manager connects the Riviera mixed-language simulator and hardware acceleration board from a single environment while the optional third-party FPGA synthesis and implementation (P and R) tools complete the flow.

The design modules are simulated, synthesised and placed into hardware.

Communication between hardware and software is managed by the DVM.

Rivera-IPT Desktop supports IEEE VHDL 1076-87/93 and Vital 2000 in addition to Verilog 1364-2001 and SystemVerilog.

The Riviera-IPT Desktop acceleration solution is available today based on a floating OS-independent licence that supports Unix, Windows and Linux.

Pricing starts at US $38,900 or the product can be leased for less than $25,000 per year.

It is sold directly by Aldec in the USA and by authorised international distributors worldwide.

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