Seminars tackle system-level methodologies

Aldec is to host a five-city seminar series on system-level methodologies.

Aldec is to host a five-city seminar series on system-level methodologies.

The seminar series is aimed at helping engineers transition to faster verification techniques using their current design flow by providing practical approaches to system-level design.

Each seminar will be divided into two parts.

The morning session will cover the SystemC methodology as well as implementation strategies for incorporating it into current design flows.

In addition, lunch will be provided for those who would like to stay for a demonstration of Aldec's coverification solution using the ARM processors.

The afternoon session will provide hands-on training using SystemC and will provide the opportunity to practice writing high-level test benches and other transaction-level modelling techniques.

A fee of US $99 will include design software, course materials including tutorials, and additional sample designs for engineers to take and review at a later date.

Aldec will also be hosting special keynote speakers in select cities.

The seminar tour will stop in the following cities: Ottawa, Canada, 8th September 2004; Boston, Massachusetts, 16th September 2004; San Jose, California, 30th September 2004; Dallas, Texas, 12th October 2004; and Austin, Texas, 13th October 2004.

"This seminar series is another example of Aldec's commitment to supporting continuing education for ASIC and FPGA designers interested in new design and verification techniques", said Eric Seabrook, Product Marketing Manager at Aldec.

"Our goal with this series is to continue to proliferate the ease of use of system-level design languages such as SystemC while maintaining current RTL".

Back to top