Product category:
Design and Development Software
News Release from: Aldec | Subject: Active-HDL 6.3
Edited by the Electronicstalk Editorial
Team on 20 October 2004
Software supports native SystemC
cosimulation
The latest version of Active-HDL incorporates a direct simulation kernel connection to SystemC, as well as an all new accelerated waveform viewer.
The latest version of Active-HDL incorporates a direct simulation kernel connection to SystemC, as well as an all new accelerated waveform viewer, creating a highly efficient cosimulation and debugging environment for electronic system-level design and verification Aldec has implemented a direct kernel connection between Active-HDL's mixed-language VHDL and Verilog HDL compilers and the C/C++ compiler providing a seamless cosimulation environment for SystemC, independent of the entry language
This article was originally published on Electronicstalk on 26 Jan 2005 at 8.00am (UK)
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Design software is made for Altera
Available now from Aldec, Active-HDL 6.3, Altera Edition features direct support and automation for Altera's Quartus II design software version 4.2, Stratix II FPGAs and HardCopy II structured ASICs.
Software does the lot for Actel FPGAs
Aldec has released a special Actel Edition of Active-HDL 6.3, offering easy-to-use pushbutton integration with Actel's Designer series advanced place-and-route software.
This was previously accomplished only through slower communication interfaces such as PLI/VPI.
Active-HDL allows the engineer's design and verification tools to create SystemC modules and then compile and cosimulate them using the external C compiler without unnecessary overhead.
Results of the cosimulation can be examined in Active-HDL's all new waveform viewer and debugging environment by one of two ways - either using Active-HDL's toolsuite which includes a built-in C debugger, or by using the engineers choice of external debugging tools.
Further reading
Interface streamlines FPGA design flow
Aldec and Magma Design Automation have completed the design flow interface between Active-HDL 6.3 and Palace version 2.4.
Design software spots problems early on
Alint gives engineers instant feedback on structural, coding and consistency problems early in the design verification cycle.
FPGA board prototypes space designs
Flash-based prototyping board eases application of radiation-tolerant antifuse-based RTAX-S FPGAs from Actel.
Active-HDL 6.3 includes several sample designs that illustrate the advantages of using SystemC with HDL as well as the benefits that electronic system-level verification engineers can obtain from such an approach.
In addition to the native cosimulation, Active-HDL includes a transaction-level testbench wizard to help automate and assist design engineers with testbench generation.
The wizard generates SystemC files that can be used as a starting point for the development of transactional testbenches.
Once generated these templates can be modified and executed through Active-HDL's GUI-based testbench wizard.
Aldec has completely redesigned the waveform viewer in Active-HDL 6.3 based on a new database and compression technique that enables viewing and managing of large files (1Gbyte and larger) almost instantaneously.
Active-HDL can read and write from the waveform database at speeds never before achieved while decreasing system memory requirements.
For example, in tests, simulating with full-signal history resulted in as much as a 2x reduction in system memory and a 10x speed-up in viewing.
Designers can open, zoom, and scroll large files instantly.
Signals, including Verilog memories or large VHDL records, can be expanded without delay.
Although the format is optimised specifically for large designs and long simulation runs, the performance increase can be seen in all aspects of the waveform viewer.
"Redesigning the waveform viewer in Active-HDL 6.3 has dramatically decreased large file management tasks.
Files that used to require minutes, or even hours to open and navigate can now be accomplished in seconds", stated Eric Seabrook, Product Marketing Manager for Aldec.
Seabrook added: "As designs continue to grow, the need to develop faster tools and methods for managing them is just as important".
"This waveform viewer is simply one of the fastest on the market".
Active-HDL conforms to IEEE standards for VHDL and Verilog and provides a complete FPGA vendor-independent solution.
Active-HDL 6.3, which is available today, includes a multi-design workspace, HDL editor, state machine editor, block diagram and schematic editors, automatic testbench generation, simulation design profiler, signal agent, waveform viewer, SystemC and a choice of VHDL, Verilog or mixed-VHDL/Verilog/EDIF simulation.
Active-HDL 6.3 is sold directly from Aldec and all sales include one year of product maintenance.
A free evaluation copy of Active-HDL 6.3 is available from the company's website.
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