Most easy to use accolade for simulator

Aldec's Active-HDL product has been selected as the most easy-to-use HDL simulator with the best price for its value.

Aldec, a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced that its Active-HDL product has been selected as the most easy-to-use HDL simulator with the best price for its value.

The award was part of the first annual FPGA Journal Awards sponsored by FPGA and Programmable Logic Journal.

Award winners were selected based on feedback from design engineers in several formal surveys and studies held over the course of the year.

Users responded that Aldec's simulator was extremely approachable and easy to learn.

In addition, they highlighted the company's whole-solution approach to simulation and debug and its clear focus on FPGA design in particular.

Readers also found Aldec's tools to be an outstanding value for the price.

The primary data for determining the winners came from online user surveys of completed FPGA projects.

Respondents were those who had completed a real FPGA project within the past year, and answers were tabulated based on responses related to those completed projects.

Readers were asked to rank the importance of a number of factors in choosing their tools and the vendors that sold them.

We then asked you to rate how well your particular vendors and products performed in each of those categories.

To see more on how the survey was completed, please visit: www.fpgajournal.com.

"It is gratifying to be publicly recognized with this award for something that Aldec has always strived to provide its customers - to make design and verification as simple as possible," stated Eric Seabrook, product marketing manager for Aldec.

"We provide a tool for the majority of the industry, namely those engineers that would rather be thinking about the design and not worrying about the language or methodology that is required to make it happen.

There couldn't be a higher honor than being recognized for this award by the users themselves." Easy-to-Use Software Based on Automation and Wizards Active-HDL offers many capabilities designed for ease-of-use.

This is visible through Active-HDL's automated graphical design flow and project manager which are changeable to vendor specific design flows.

In addition, Active-HDL also contains many design capture and debug options together with a high-performance, mixed VHDL, Verilog, and SystemC simulator.

The product also has many built-in wizards and automated task capabilities that make up the graphical user interface of the tool.

Tools like the Testbench Wizard, VHPI/PLI Wizard, and soon-to-come Assertion Wizard that will allow the design engineer to easily author and implement OVA and PSL Assertions into the design without requiring designers to have in-depth understanding of the language.

Complete Design and Verification Having all the capabilities for design capture, mixed simulation and debugging in one complete suite is the real benefit of the solution.

Using separate vendors means managing many different pieces of a design flow.

Active-HDL automates this process through the project manager and is integrated to most third-party synthesis and place and route tools on the market providing push button functionality.

This leaves much less for the engineer to manage and makes updating and maintenance even easier.

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