Product category:
Design and Development Software
News Release from: Aldec | Subject: Active-HDL 6.3
Edited by the Electronicstalk Editorial
Team on 18 November 2004
Interface streamlines FPGA design flow
Aldec and Magma Design Automation have completed the design flow interface between Active-HDL 6.3 and Palace version 2.4.
Aldec and Magma Design Automation have completed the design flow interface between Active-HDL 6.3 and Palace version 2.4 The integration of the two products automates the data exchange of graphical design capture, mixed VHDL and Verilog verification and physical synthesis providing an efficient, easy-to use solution for Actel, Altera and Xilinx designs
This article was originally published on Electronicstalk on 26 Jan 2005 at 8.00am (UK)
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Design software is made for Altera
Available now from Aldec, Active-HDL 6.3, Altera Edition features direct support and automation for Altera's Quartus II design software version 4.2, Stratix II FPGAs and HardCopy II structured ASICs.
Software does the lot for Actel FPGAs
Aldec has released a special Actel Edition of Active-HDL 6.3, offering easy-to-use pushbutton integration with Actel's Designer series advanced place-and-route software.
Aldec and Magma have worked together to implement a new design flow option in Active-HDL to utilise the functionality of Palace for physical synthesis of FPGA designs.
When the design flow for the physical synthesis tool is enabled, a window displays the physical synthesis option button that allows the designer to control the process performed by Palace.
When combined with the FPGA vendor-supplied or industry-supplied FPGA synthesis tools, Active-HDL and Palace provide a fully integrated front-to-back tool flow that delivers higher quality results.
"The interface between Active-HDL and Palace provides complete design flow management of large FPGA and PLDs, independent of the architecture", stated Eric Seabrook, Product Marketing Manager for Aldec.
Seabrook added: "As designs continue to grow in complexity and FPGA users are becoming faced with the challenge of ASIC like flows an automated data exchange between the tools becomes increasingly important".
Whereas Palace focuses on optimisation of the synthesised netlist and architecture-specific implementation, Active-HDL provides a graphical design capture, mixed-HDL simulation and debugging environment.
Once the design is verified in Active-HDL, the RTL is synthesised and optimised using Palace through the automated design flow manager.
"Aldec provides FPGA designers with a highly integrated environment to capture and verify designs", said Behrooz Zahiri, Director of Product Marketing at Magma.
"Through Magma's and Aldec's collaboration, FPGA designers familiar with the Active-HDL verification and design flow can now take advantage of Palace's advanced physical synthesis and speed-grade improvements".
Active-HDL conforms to IEEE standards for VHDL and Verilog and provides a complete FPGA vendor independent solution.
Active-HDL 6.3 has a starting price of less than $6000 including the interface to Palace, and is sold directly by Aldec in the USA and by authorised international distributors.
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