Product category:
Design and Development Software
News Release from: Aldec | Subject: Active-HDL 6.3, Altera Edition
Edited by the Electronicstalk Editorial
Team on 26 January 2005
Design software is made for Altera
Available now from Aldec, Active-HDL 6.3, Altera Edition features direct support and automation for Altera's Quartus II design software version 4.2, Stratix II FPGAs and HardCopy II structured ASICs.
Available now from Aldec, Active-HDL 6.3, Altera Edition features direct support and automation for Altera's Quartus II design software version 4.2, Stratix II FPGAs and HardCopy II structured ASICs Aldec has developed a TCL-based script that automates the design flow interface between Active-HDL and the Quartus II software
This article was originally published on Electronicstalk on 21 May 2003 at 8.00am (UK)
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This automated solution from Aldec and Altera provides the engineer with a closed design environment while delivering complete access to compile and simulate FPGA and HardCopy structured ASIC devices from a single design environment.
"Active-HDL's Altera Edition with Quartus II software support provides the designer with full access to unlimited simulation and debugging capabilities for FPGA and structured ASIC designs in an easy-to-use environment", stated Chris Erwin, Product Marketing Manager for Aldec.
Erwin added, "The automated design flow manager, along with precompiled Altera libraries and access to several popular synthesis tools, completes the solution".
"Active-HDL, Altera Edition and Quartus II software provide a cohesive design solution for customers targeting high-performance Stratix II devices".
"This design solution is also applicable to the recently announced HardCopy II structured ASIC", said Jim Smith, Director of EDA Vendor Relations at Altera Corp.
Active-HDL's design flow manager handles the entire process from design capture through synthesis, implementation and optimisation including a direct link to the Altera Megafunctions Wizard.
The Altera Quartus II physical implementation tools can be easily be accessed and automated by the design flow manager and provides centralised error message handling with direct access to the synthesis and implementation reporting.
Active-HDL's memory viewer can also read and save Altera memory initialisation files.
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