Coverification and debug takes on ARM hard core

Aldec has released Riviera-IPT with all-new support for the ARM926 hard-core processor including functionality for smart clocking and memory mapping.

Aldec has released Riviera-IPT with all-new support for the ARM926 hard-core processor including functionality for smart clocking and memory mapping.

Riviera-IPT provides a seamless, high-speed coverification and debug environment for today's most complex embedded software/hardware system-designs using ARM.

Riviera-IPT with ARM provides a hardware accelerated simulation of the ARM926 processor integrated with a software debugging environment that results in a complete high-speed coverification platform.

The ARM hardware processor model ensures the highest verification accuracy with debugging, similar to emulation systems, while the acceleration speeds the peripheral simulation time.

This hardware/software combination leads to the most efficient co-verification solution available.

Riviera-IPT now includes support for the ARM 926 EJ-S integrator board, providing access to the actual processor used in the most popular platform-based OS devices such as new generation smart phones, communicators, PDAs, digital cameras and A/V decoders.

The hard-core processor and integrator board connect directly to the Riviera-IPT accelerator and both are controlled by the Design Verification Manager (DVM).

Riviera-IPT's Design Verification Manager connects the HDL simulator, software debugger, acceleration board and the ARM processor from a single environment and provides the designer with easy access to all logic states for analysis and debug.

Standard hardware debugging is provided via Riviera, and the ARM processor uses the standard ARM debugging software.

A new smart clocking mode is available in Riviera-IPT.

Smart clocking is a switching mechanism for the ARM processor allowing the designer to combine emulation speed with simulation functionality.

The Amba bus works with the hardware clock to ensure the highest verification speed while simultaneously switching between the software clock (delivered from the testbench) when it is required by the system.

This occurs while debugging the peripherals in the software simulator.

The clock switching mechanism provides the engineer with dynamic peripheral configuration for simulation, either with software or hardware, for increased efficiency.

Riviera-IPT also includes support for memory mapping and partitioning to physical onboard memories.

This extended memory support allows the designer to emulate various RAM architectures in a single device while at the same time substantially reducing the simulator overhead that would normally be required to handle these memories.

It also allows the simulator to verify the entire memory space in a shorter amount of time.

As much as 12Gbyte of RAM is available for emulation of the most popular DDRs, SRAMs and SDRAMs.

"Using the new generation of Riviera-IPT with ARM provides design teams with a new level of control and functionality while substantially reducing the verification time", stated Eric Seabrook, Director of Marketing for Aldec.

"Riviera-IPT combines the best in an HDL simulator with software debug, hardware acceleration as well as a processor in a seamless environment", Seabrook added.

Riviera-IPT 2004.12 with ARM is available today based on a floating OS-independent licence that supports Unix, Windows and Linux.

Pricing starts at $90,000 for one year, or the product can be leased per quarter.

It is sold directly by Aldec in the USA and by authorised international distributors.

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