New technology speeds system-level verification

The latest release of Riviera features an all new system-level simulation engine and improved SystemC debugging.

Aldec has released Riviera 2005.04 with an all new system-level simulation engine and improved SystemC debugging.

Riviera is based on Aldec's industry-proven VHDL and Verilog mixed-language simulation technology used by ASIC and high-density FPGA designers for new generation system-on-chip designs.

Riviera 2005.04 includes an all new simulation technology designed for use in system-level verification.

The system-level platform (SLP) incorporates a completely redesigned simulation engine that dramatically reduces simulation run times for gate-level and timing verification.

This new simulation technology integrates seamlessly with the current environment and is completely transparent to the designer.

Riviera with SLP will simulate any designs containing Verilog netlists and automatically distribute simulation tasks between the new SLP engine and the standard simulation engine.

In addition to the Verilog performance, the new release has decreased VHDL timing simulation runtimes by as much as 3x through further optimisation of the Vital libraries.

Riviera 2005.04 has extended the support for SystemC, now allowing a history of the SystemC signal to be stored and displayed from the Riviera simulation database (.asdb).

Signal breakpoints can be set on SystemC signals for value, event, and transaction.

The latest release also includes a pre-installed gcc package and precompiled SystemC Verification libraries (SCV) to simplify the setup.

"The increased Verilog and VHDL simulation performance of Riviera 2005.04 will provide an enormous gain to our already industry standardised simulation performance", stated Eric Seabrook, Director of Marketing for Aldec.

"Adding the improvements for cosimulation with SystemC and Matlab provides a completely new level of support from Aldec for system-level design".

In addition to the Simulink interface, Riviera now offers the ability to cosimulate directly with Matlab.

The interface bridges the gap between the mathematical computation, analysis, visualisation, algorithm development environment and the HDL hardware modelling and simulation environment.

It allows for direct calling and visualisation of any built-in or M-language functions from Verilog or VHDL.

All three assertion languages including OpenVera assertions (OVA), Property Specification Language (PSL) and SystemVerilog assertions (SVA) have been improved for both VHDL and Verilog.

Riviera 2005.04 also includes the ability to generate VCD output for VHDL providing engineers with an industry standard printing format of the simulation results.

Riviera 2005.04 is available today based on a floating OS-independent licence that supports Unix, Windows and Linux.

Pricing for Riviera 2005.04 begins at US $12,450.00 and is sold directly by Aldec in the USA as well as by authorised international distributors.

A free evaluation copy is available from the Aldec website.

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