Simulator made for networked design verification

Riviera-SNA addresses changing customer needs as ESL and ASIC manufacturers require an increased number of high-performance simulators online.

Aldec has released Riviera-SNA (simulator for networking applications).

The new product is aimed at 64bit Linux design verification server farms and is priced starting at less than $200 per seat.

Riviera-SNA addresses changing customer needs as ESL and ASIC manufacturers require an increased number of high-performance simulators online.

Despite that over 70% of the design effort goes into design verification alone, there are still many ASIC respins and product cancellations due to poor design quality.

To cope with these issues, the industry has seen a surge in automatic testbench generation tools.

This surge has caused an explosion in the number of testbenches and, in turn, simulation time needed for verification.

Because of this, current simulation farms with access to 100-500 simulators can no longer do a satisfactory job.

The ESL, ASIC and large consumer goods manufacturers now need farms with 1000 to 10,000 (or more) high performance simulators online.

"A paradigm shift is taking place in design verification".

"Existing limitations to corporate simulator networks are becoming the next bottleneck in the design process", stated Stanley Hyduke, President of Aldec: "Because tools such as Synopsys Vera and Cadence Specman Elite are being increasingly used for automatic testbench generation,engineers now need a way to verify hundreds, or even thousands, of testbenches in a fast and economical way".

"Simulation is entering a new phase as the primary product quality assurance tool", stated Eric Seabrook, Director of Marketing for Aldec.

He added: "Riviera-SNA is a simulator product for networking applications that makes economical sense for the new era of automatic testbench generation".

"Riviera-SNA will be well-suited for simulation farms at medical, military, communications and consumer goods manufacturers".

Riviera-SNA is a batch mode, common kernel, multilanguage simulator.

Based on Aldec's industry-proven VHDL and Verilog mixed-language simulation technology, the new product is aimed at supporting large verification teams seeking access to an unlimited number of simulators.

Aldec has also added major gate and timing simulation speed enhancements to Riviera-SNA to allow even faster functional and timing design verification.

Riviera-SNA currently runs on AMD Opteron 64 with support for Solaris10 to follow shortly.

It handles VHDL, Verilog, SystemVerilog and SystemC mixed designs with support for PSL, OVA and SVA assertions.

The product enables large multinational companies to simulate more than 50,000 test cases within a 12 hour period at a very low cost.

Aldec is currently installing Riviera-SNA on a 10,000-node server farm for a renowned ASIC manufacturer that is supplying electronic devices to the automotive and wireless industries.

This installation is the largest design verification server farm in the electronics industry.

The installation should be completed and tested within the next month, a separate announcement will follow.

Riviera-SNA is available now and is sold directly by Aldec in the USA as well as by authorised international distributors.

The single language Riviera-SNA sells for $180 each as 1-year licence in quantities of 10,000.

In quantities of 1000 pieces Riviera-SNA is under $400 each.

Mixed language support is also available at an additional cost.

A free evaluation copy of the basic Riviera is available from the Aldec website.

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