HDL simulator supports multicore SPARC

Edited by the Electronicstalk editorial team May 5, 2006

Aldec is providing full simulation support in Riviera for the open-source UltraSPARC T1 from Sun Microsystems.

Aldec is providing full simulation support in Riviera for the open-source UltraSPARC T1 from Sun Microsystems.

Riviera, a world-class mixed language HDL simulator, supports common kernel simulation of complex digital logic circuit designs that have been written in Hardware Description Languages (HDL), including VHDL, Verilog, SystemVerilog and SystemC.

"Aldec looks forward to the many new possibilities and applications that the OpenSPARC community will develop".

"We are offering the utilisation of Aldec's Sun Solaris based Riviera simulator at no cost for 90 days to all qualified organisations that drive the art and science of multicore, multithreaded hardware and software design", said David Rinehart, Vice President of Marketing at Aldec.

Sun Microsystems has released its UltraSPARC T1 multicore processor to the general public.

Sun's initiative will allow the OpenSPARC community to implement custom logic circuit hardware designs using the OpenSPARC T1 Verilog source code model of the UltraSPARC T1.

To support this effort, Aldec will offer free access to its Riviera Verilog Simulator on the Sun Solaris 10 platform for a 90-day trial basis to all qualified organisations.