SoC simulator supports IP encryption

Aldec is providing support for the Open IP Encryption Initiative design flow in the latest version of its Riviera tool.

Aldec is providing support for the Open IP Encryption Initiative design flow in the latest version of its Riviera tool.

The Open IP Encryption Initiative is a nonproprietary IP encryption methodology authored by Synplicity.

Synplicity has worked with Aldec to support this new methodology of handling IP (intellectual property) encryption in simulation and synthesis.

Lack of an industry-wide standard for IP encryption and decryption has concerned both IP vendors and their customers for a long period of time.

While easy to use, unencrypted IP cores were prohibitively expensive for some customers, and availability of cheaper (but encrypted) versions working with customer tools was spotty.

Maintaining multiple IP core versions for multiple tools was also cumbersome for IP vendors.

With built-in support for the new Open IP Encryption flow, engineers can easily compile, simulate and synthesise, Verilog encrypted IP with Synplicity's Synplify and Synplify Pro FPGA synthesis software and Aldec's Riviera tools.

"Aldec's support for the Open IP Encryption Initiative will help to create a front-to-back design capability with comprehensive encrypted IP support", said Andy Haines, Senior Vice President of Marketing at Synplicity.

"Users of Aldec's Riviera product will be amongst the first to benefit from a truly open and easy-to-implement IP protection scheme where all tools will be able to analyse and optimise the IP source code in the same way as unencrypted source code".

Simulation of encrypted Verilog sources based on Synplicity's Open IP Encryption Initiative methodology is now available in the new release of Aldec's Riviera 2006.06 high performance SoC simulator.

The flow is compatible with the recently published Verilog standard IEEE1364-2005 and forthcoming VHDL 2006 standard.

It enables easy encryption of any fragments of IP cores for secure delivery from the IP vendor to the customer.

The encryption involves no action on the side of the customer - all required activities involve IP vendor and tool vendors only.

Customers can open delivered IP source but will only see unintelligible, encrypted and encoded text.

The Riviera compiler will be able to decrypt the source on-the-fly, leaving no traces that could compromise the security of encryption.

Additional improvements in Riviera 2006.06 include: faster Verilog and VHDL compilation and simulation; PSL assertions embedded in VHDL code for improved verification, communication and IP correct usage detection; Expression Coverage for fine grained statistics analysis of testbench effectiveness; and numerous GUI enhancements.

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