HDL simulator upgrades performance

The latest Riviera-Pro release adds high performance SLP (system level platform) technology and is an important milestone for Aldec in Verilog RTL, gate and timing simulation.

New from Aldec is the Riviera-Pro 2006.10 HDL simulator.

This release adds the high performance SLP (system level platform) technology and is an important milestone for Aldec in Verilog RTL, gate and timing simulation.

Customers that currently own Riviera-Pro will see an average performance gain of 57% on their RTL and 250% on gate level and timing simulations over previous releases of the software.

Riviera-Pro adds the ability to use generics (parameters) in instantiations of SystemC modules in VHDL or Verilog code and HDL block instantiations within SystemC code.

Visibility of SystemC objects in debugging windows is also improved.

Support for Microsoft Visual Studio 8.0 (Windows platform) and newer versions of gcc compilers is available.

Support for SystemVerilog (IEEE1800-2005) and PSL (IEEE1850-2005) is extended in this release of Riviera-Pro.

The enhancements should affect both testbenches and design code.

Numerous improvements have been made to the existing functionality of Riviera-Pro and new features requested by users have been implemented in the waveform viewer including better zooming and scrolling, more alignment options, easier access to search options and support for new waveform formats.

Users of expression coverage can now better control analysed hierarchical regions of the design and merge data from different sessions.

In addition, new signals can be added to toggle coverage during the simulation session.

Finally, Xtrace can be linked with advance dataflow, allowing better visualisation of distribution of the irregular values.

Open IP encryption (originally developed by Synplicity) is now available for VHDL code in addition to previously available Verilog code encryption.

Several new commands and new arguments of the existing commands are also now supported, and compilation times and memory usage for VHDL and Verilog are significantly reduced.

"Aldec's engineering team has worked extremely hard to upgrade our Verilog simulator to include the new SLP simulation technology".

"In this release we have seen measurable performance gains at customer sites on ASIC and large FPGA designs at all three levels of verification", commented Dave Rinehart, Vice President Aldec.

"Additional optimisations will be preformed in subsequent releases providing even greater performance gains especially in areas of SystemVerilog (IEEE1800)".

Riviera 2006.10 is available today in two configurations Riviera-SE and Riviera-Pro, all licences are floating and support Unix, Windows and Linux.

The product is sold directly by Aldec and its authorised international distributors.

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