Product category:
Design and Development Software
News Release from: Aldec | Subject: System Verification Environment
Edited by the Electronicstalk Editorial
Team on 10 November 2006
Verification environment moves up to
Stratix III
Aldec has announced System Verification Environment (SVE) support for Altera Corporation's new high-end Stratix III FPGA device family.
Aldec has announced System Verification Environment (SVE) support for Altera Corporation's new high-end Stratix III FPGA device family SVE supports all aspects of system-level design development and verification
This article was originally published on Electronicstalk on 21 May 2003 at 8.00am (UK)
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"Aldec and Altera engineering teams are working together to ensure Aldec's verification solutions are validated for Stratix III device support".
"The integration of Altera's Quartus II design environment to Aldec's mixed-language verification solutions provide customers with a seamless migration path for validating Stratix III designs", stated Dr Stanley M Hyduke, CEO of Aldec.
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"The relationship between our companies continues to grow and we look forward to supporting our mutual customers on the next generation of Stratix designs".
"Engineers designing with Stratix III devices have a broad range of system-level requirements, including intellectual property integration and multilanguage support".
"In addition to meeting these requirements, Stratix III devices can accommodate multiple processors, memories and peripheral devices", said Danny Biran, Vice President of Product and Corporate Marketing at Altera.
"Engineers can then use the Aldec SVE solution to accelerate the verification cycle for their Stratix III designs".
To speed verification and debugging of Stratix III designs, SVE can also handle OVA, PSL and SVA (System Verilog) assertion languages.
Language templates and predefined test suites ease testing requirements for system-level designs.
The newest trend in design automation is the use of code coverage driven intelligent test benches.
However, such test benches require a considerably larger number of simulators than the traditional test benches.
To handle a large number of test vectors and simulation results, Aldec has developed a server farm manager for Stratix III FPGAs capable of handling thousands of simulators in a highly efficient manner over corporate networks.
The SFM performs numerous operations and functions on design files such as running complex flows on multiple machines, storing, managing and comparing verification results, providing error reports and statistical summaries, optimising license utilisation, automatic network reconfiguration in case of failed nodes, and optimising the usage of corporate computer power.
The SFM option runs on 64bit Linux simulation server farms and handles mixed designs and test benches written in VHDL, Verilog, SystemVerilog and SystemC.
"We place special attention to handling large designs in the most economical way to meet the needs of designers using Stratix III devices".
"This is why we developed full automation of the design verification process based on a powerful simulation server farm manager", commented Dr Hyduke.
SVE cosimulates EDIF netlist blocks with HDL RTL blocks that allow use of legacy modules with Stratix III devices.
Such capability is unique to Aldec's common kernel HDL verification environment and allows unlimited switching of legacy FPGA designs to the newest silicon from Altera.
SVE will be available in January 2007, and will incorporate system-level verification products to facilitate validation of high-end Stratix III devices.
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