New interface simplifies design verification

Edited by the Electronicstalk editorial team Apr 12, 2007

Co-simulation support for fixed-point in Simulink simplifies verification of hardware designs in Active-HDL.

Aldec, a specialist developer of mixed-language simulation and design tools for ASIC and FPGA devices, has released cosimulation support for fixed-point in Simulink.

Active-HDL coupled with The MathWorks Simulink provides support for fixed-point types and HDL cosimulation of black-boxes, which allows seamless integration with Simulink-based DSP tools.

Aldec's new Simulink Interface simplifies verification of hardware designs in Active-HDL through robust data visualisations and several advanced design-analysis tools.

It provides for direct co-simulation of mathematical and HDL hardware components of system-level designs.

The interface allows successive replacement of mathematical models describing the system operation with their equivalent target HDL components.

The interface also reduces time to market by filling the gap between high-level abstraction of algorithmic modeling and FPGA and ASIC-oriented low-level hardware modeling.

The Simulink Interface is provided as part of the standard Active-HDL (PE and EE) configuration for no additional charge.

The interface is sold as a separate add-on option for all other product configurations.