Design software spots problems early on
Alint gives engineers instant feedback on structural, coding and consistency problems early in the design verification cycle.
Aldec has released Alint 2008.06, software that compares Verilog source code against 195 design rules based on STARC 2006.
Alint gives engineers instant feedback on structural, coding and consistency problems early in the design verification cycle.
New enhancements to Alint 2008.06 include the addition of 15 new STARC rules, a new GUI including an advanced violation viewer, configuration manager and dedicated clock domain crossing (CDC) rule-sets.
Alint offers a solution for clock and reset analysis, detecting potential clock domain crossing (CDC) issues.
Combinational logic between asynchronous clock domains can lead to metastable conditions, which in turn lead to circuit malfunctioning.
Alint detects whether or not the designer located combinational logic between asynchronous clock domains.
Clock violations can be detected early in the verification process aiding clock line balancing, timing analysis and correct clock data.
Alint includes a standalone application, the Violation Viewer, which allows engineers to view all violations that occur in the source code and cross-probe to any HDL editor.
Double-clicking on any violation reported in the violation viewer cross-probes directly to the line of Verilog source code that caused the violation.
All violations are sorted by their type, files-modules-rule-sets or rules and are printable.
Rules and rule descriptions are displayed in association with each violation.
A summary of all violations can be viewed within the violation viewer at all times.
The Configuration Manager enables engineers to use existing pre-defined rule sets and policies or create custom rule sets, selecting or de-selecting rules from the master list of 195 STARC-based design rules.
Rules can be combined within the configuration manager to form rule-sets and policies that are treated by Alint as a single object.
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