New name in coverification for SoC designs

Adveda is a new Netherlands-based provider of software for the functional verification of both hardware and software, which merges the hardware and the software developments of an SoC design.

Adveda is a new Netherlands-based provider of software for the functional verification of both hardware and software, which merges the hardware and the software developments of an SoC design.

"Today, all SOCs contain one or more processors, a lot of memory and a varying amount of additional logic, while the amount of software running on these processors is increasing dramatically.

The embedded software is also increasingly influencing the hardware, thus requiring that both hardware and software must be verified together before putting the design into silicon", observes Cor Schepens, Adveda's Chief Executive Officer (CEO).

The EDA industry has traditionally tried to solve the hardware software verification problem by building interfaces between existing tools, creating unnecessary constraints and bottlenecks for designers.

Instead, for true hardware/software codesign and coverification, the hardware and embedded software of SoC designs should be verified in one integrated environment.

Cor Schepens serves as Adveda's CEO and has 17 years experience in the ASIC and EDA industry.

Before founding Adveda, Schepens was responsible for marketing and sales at Adelante Technologies, an embedded DSP vendor.

Prior to this, he was European Sales Manager at Frontier Design, a behavioural synthesis software company.

He had previously worked in various sales positions at Mentor Graphics in Germany.

Additionally, Schepens has extensive direct ASIC and FPGA design experience.

He holds a MS in electronics from the Technical University of Eindhoven.

Huub Erens serves as Adveda's CFO.

He is also the owner of the Qualitech consortium and has 30 years of experience in the electronics industry.

Erens has a MS in law from the University of Utrecht and also holds a MS in electronics from the Technical University of Eindhoven.

Henk Aerts is CTO at Adveda.

For the last 13 years he has worked as an independent software architect consultant for various companies.

Prior to this, he was CTO at Bohm and also developed software at Burroughs/Unisys.

He is the architect behind Adveda's ISS and debug technology, and has designed a variety of application software, compilers, assemblers, operating systems, debuggers and simulators on many different processors.

Marc Seutter serves as Chief Architect of hardware tools.

Seutter worked as a Senior System Designer at SPaSE, an ASIC design house, for several years, responsible for one of the first HW/SW coverification strategies.

He has a PhD in mathematics and informatics from the University of Nijmegen and is the inventor of the fast RTL simulation tools.

His PhD thesis was about formal hardware description languages.

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