Product category:
Design and Development Software
News Release from: Adveda | Subject: Univers Modeler
Edited by the Electronicstalk Editorial
Team on 02 June 2004
SystemC models run faster than RTL
The Univers Modeler is an extension to Adveda's ultra-fast RTL simulator, which generates a SystemC wrapper or a PLI/FMI wrapper around a native simulation model, compiled within this simulator.
The Univers Modeler is an extension to Adveda's ultra-fast RTL simulator, which generates a SystemC wrapper or a PLI/FMI wrapper around a native simulation model, compiled within this simulator This allows users up to 100 times faster simulation speeds within their own simulation environment through its PLI, FMI or SystemC interface
This article was originally published on Electronicstalk on 4 Feb 2004 at 8.00am (UK)
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Univers Modeler takes the original RTL-code and converts it automatically to a cycle-accurate simulation model at a higher level of abstraction, wrapped in SystemC.
The generated model runs faster than an RTL simulation, similar to the speed reached with manually written SystemC models.
Using Univers Modeler saves designers many man months of writing models by hand.
It also guarantees correct functional and cycle-accurate behaviour, allowing designers to debug their real RTL design rather than just a model of the design.
The Univers Modeler can also wrap these models with a PLI or FMI interface, allowing the models to be used within existing RTL simulators.
It handles the full synthesisable RTL syntax, including multiple asynchronous clocks, asynchronous resets as well as tristate signals.
The first production release will support the VHDL RTL language, and is available immediately.
"A growing number of designers are looking at SystemC modelling as a way to speed up their verification process".
"With the Univers Modeler, designers can take immediate advantage of fast SystemC models without any change in their design flow", said Cor Schepens, Adveda's CEO.
"IP vendors will benefit from the fact that the fast simulation models are also optimally encrypted, leaving them the option to determine the internal signals which are visible for the end-user".
The Univers hardware software coverification solution combines fast hardware simulation and fast instruction set simulators (ISS) using a unique architecture, which employs only one simulation kernel in a unified development environment.
This next-generation approach results in unsurpassed coverification speeds and unique debug features.
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