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Azuro
100 View Street
Suite 200
Mountain View
CA 94041
USA
Latest articles from this company
News releases from this company
Clock tree synthesis passes nanometre GPU test
Successful evaluation demonstrates PowerCentric's ability to reduce power and also meet complex variability-driven clock tree implementation requirements.
News from Electronicstalk, 1 June 2007
Clock tree synthesis and optimisation unite
PowerCentric brings together unique algorithms for clock tree buffering, gate-level clock gate logic synthesis and statistical average-case dynamic power analysis.
News from Electronicstalk, 31 May 2007
Low power methodology aids ARC designs
Azuro's PowerCentric low power methodology now is available for ARC licensees designing audio- or video-centric digital chips for embedded applications.
News from Electronicstalk, 21 July 2006
Clocking software cuts CSR chip consumption
CSR has successfully taped-out its first design using Azuro's PowerCentric clock implementation solution.
News from Electronicstalk, 17 July 2006
Low power clocking software goes below 65nm
PowerCentric version 3 extends its 15-25% power reduction capabilities to support advanced variability-aware design flows at 65nm and below.
News from Electronicstalk, 7 July 2006
Mauskar and Almusa target expansion
Azuro has added two new executives to its management team, signalling further expansion for following the company's entry into the Japanese market last month.
News from Electronicstalk, 27 February 2006
KeyBridge to support Japanese sales
Azuro has selected KeyBridge to provide sales support in Japan for its innovative EDA tools that significantly reduce the power consumption of digital ICs.
News from Electronicstalk, 25 January 2006
New funds to enable Azuro expansion
Azuro has raised $9 million in second round venture funding.
News from Electronicstalk, 6 January 2006
EDA startup focuses on wireless power cuts
Azuro has revealed its strategy to deliver next-generation design tools that attack the growing power rift in digital chip design.
News from Electronicstalk, 17 May 2005
Vectorless estimation enables IC power cuts
A revolutionary new low power clock implementation solution is claimed to significantly reduce the power consumption of digital chips.
News from Electronicstalk, 17 May 2005
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