EDA startup focuses on wireless power cuts

Azuro has revealed its strategy to deliver next-generation design tools that attack the growing power rift in digital chip design.

Azuro has revealed its strategy to deliver next-generation design tools that attack the growing power rift in digital chip design.

The company is initially targeting manufacturers of next-generation wireless devices with its first product, PowerCentric.

"The wireless device market is evolving extremely fast, driven by short product lifecycles and rapidly increasing functionality", said Paul Cunningham, cofounder and Chief Executive Officer at Azuro.

"The consumer's insatiable appetite for more talk time, more play time, and increased functionality, in ever smaller packages, has elevated power to the key issue for many digital chip design teams".

"Azuro is committed to helping these design teams significantly reduce the power consumption of their chips".

To win in power-sensitive markets, chip design teams need to deliver the lowest power at the lowest price with the best functionality.

As competition in these markets has intensified, existing industry design tools have been unable to keep pace with the aggressive tradeoffs that design teams need to make between power, performance, and cost to deliver a winning product.

"Power tools have become as important, if not more important, than timing tools".

"Intel sees power as its number-one problem in the future", said Gary Smith, Chief Analyst at Gartner/Dataquest.

Azuro's first product, PowerCentric, targets the clock power problem in digital chip design.

Without careful power management, the clock network can account for as much as 80% of on-chip switching power.

PowerCentric delivers a fully unified low-power clock implementation solution that significantly reduces on-chip switching power above and beyond existing low power industry solutions.

Azuro's customers can translate this power saving advantage directly into enhanced functionality, talk time, or play time on their devices.

"Azuro has already succeeded in working with customers to deliver low-power silicon to the market, and has built a strong management team with a potent blend of experience and creativity", said Mark Evans, General Partner at Benchmark Capital.

In addition to Cunningham, the company's management team includes: Steev Wilcox, cofounder and Chief Architect; Barb Acosta, Vice President Sales and Business Development, formerly with Get2Chip, Cadence and Synopsys; Peter Knoop, Vice President Engineering, formerly with Convergys, Geneva Technology and Alphametrics; and Mark Bagby, Chief Financial Officer, formerly with Simplex, Cadence, and Synopsys.

Azuro is headquartered in Mountain View, California and has a development office in Cambridge, UK.

The company received its Series A funding in 2003 in a round led by Benchmark Capital.

Other investors include TTP Ventures and The Cambridge Angels.

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