Vectorless estimation enables IC power cuts

A revolutionary new low power clock implementation solution is claimed to significantly reduce the power consumption of digital chips.

Azuro has released PowerCentric, a revolutionary new low power clock implementation solution that significantly reduces the power consumption of digital chips.

"Power dissipation has become increasingly important to the semiconductor industry as consumers demand ever more talk time, play time, and functionality in their next-generation mobile phones and portable devices".

"Meeting power requirements is one of the biggest challenges facing chip design teams today", said Steve Barlow, Senior Director of Engineering for Broadcom's Mobile Multimedia Products.

"Without effective clock gating, most of the active power in a typical digital logic block is consumed by the clock and registers".

"Azuro provided Broadcom with design automation tools that assisted in reducing the active power consumption of our BCM2702 mobile multimedia processor".

Azuro's PowerCentric solution differs from existing industry design flows where clock gating and clock tree synthesis are performed at two different points in the flow.

By unifying these operations at the placed gates level in the design flow, PowerCentric's patent-pending iCTS technology is able to explore a larger global solution space of clock gating topologies and make power-timing tradeoffs that are superior to current industry solutions.

When compared with the industry's existing low power design flows, PowerCentric delivers significant reductions in the dynamic power consumption of logic blocks without any impact on design performance.

"Low power clock implementation is all about managing the tradeoffs between power and timing, and these tradeoffs cannot be made in the front end of the design flow", said Paul Cunningham, cofounder and Chief Executive Officer for Azuro.

"PowerCentric delivers a truly unified clock gating and clock tree balancing engine that seamlessly replaces clock tree synthesis in existing industry design flows".

PowerCentric also includes a fully integrated vectorless active power reporting engine, eliminating the need to produce representative power testbenches before power characterising a design.

"You cannot optimise what you cannot accurately measure", explained Steev Wilcox, cofounder and Chief Architect of Azuro.

"Our SASim vectorless power estimation technology enables PowerCentric to implement the best tradeoffs and save the most power during optimisation".

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