Product category:
Design and Development Software
News Release from: Azuro | Subject: PowerCentric version 3
Edited by the Electronicstalk Editorial
Team on 07 July 2006
Low power clocking software goes below
65nm
PowerCentric version 3 extends its 15-25% power reduction capabilities to support advanced variability-aware design flows at 65nm and below.
Azuro, a provider of power reduction solutions for digital designs, has announced version 3 of its PowerCentric low power clock implementation solution PowerCentric version 3 extends the company's unique 15-25% power reduction capabilities to support advanced variability-aware design flows at 65nm and below
This article was originally published on Electronicstalk on 17 May 2005 at 8.00am (UK)
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CSR has successfully taped-out its first design using Azuro's PowerCentric clock implementation solution.
Key features for this new release include: variability-aware low power clock buffering and clock gating; global skew driven optimisation with concurrent multiple-corner constraints; automatic useful skew insertion for setup and hold timing closure; across multiple modes and corners; clock tree buffering and gating across multiple voltage islands; and a powerful GUI with advanced variability-aware clock QoR analysis capabilities.
"Clock implementation is becoming increasingly critical at nanometre geometries", said Ashutosh Mauskar, Vice President of Product Marketing of Azuro.
"If performance and gate area are all that matter then clock implementation is a well contained problem, but if power, routability, and variability are important then clock implementation becomes a critical part of the design flow".
"Using PowerCentric, Azuro's customers are able to manage all these variables during clock implementation and achieve 15% to 25% power reduction without any impact on the size or performance of their chips".
PowerCentric operates as a complete replacement for traditional clock tree synthesis (CTS) in digital ASIC design flows.
By unifying clock gate synthesis and clock tree buffering into a single physically aware optimisation engine operating at the placed-gates level in the design flow, PowerCentric is able to insert up to 3x more clock gating than current low power industry design flows.
Azuro will demonstrate PowerCentric version 3 on Booth 1928 at the 43rd Design Automation Conference in San Francisco.
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