Clocking software cuts CSR chip consumption

CSR has successfully taped-out its first design using Azuro's PowerCentric clock implementation solution.

CSR, the global provider of Bluetooth and Wi-Fi technology, has successfully taped-out using Azuro's PowerCentric clock implementation solution.

"Low power is a key driver for CSR", said James Collier, cofounder and Chief Technology Officer of CSR.

"PowerCentric fits seamlessly into our design flow and has enabled us to achieve significant reductions in the digital power consumption of our chips".

Without careful power management, the clock and registers can account for as much as 80% of on-chip digital switching power.

PowerCentric uniquely combines clock gating and clock buffering into one unified low power clock implementation solution, which completely replaces clock tree synthesis in existing industry design flows.

"Clock implementation is a critical segment of any low power design flow", said Paul Cunningham, cofounder and Chief Executive Officer of Azuro.

"PowerCentric's unique technology enables design teams to manage the aggressive tradeoffs between clock QoR and power that are necessary to deliver best-in-class low power silicon".

"We are delighted to be working with CSR and look forward to continuing to deliver significant power savings on their chips".

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