Low power methodology aids ARC designs

Azuro's PowerCentric low power methodology now is available for ARC licensees designing audio- or video-centric digital chips for embedded applications.

Azuro's PowerCentric low power methodology now is available for ARC licensees designing audio- or video-centric digital chips for embedded applications.

With the use of Azuro's PowerCentric in existing Cadence, Synopsys or Synplicity design flows, customers of the configurable ARC Media Subsystems and CPU/DSP processors can reduce power consumption of the arc-based logic by more than 20%.

This complements the existing ability of ARC licensees to achieve the industry's lowest power consumption of any 32bit configurable processor or subsystem through the use of ARC's patented ARChitect configuration tool, where unneeded elements can be eliminated to dramatically reduce power usage.

Results were achieved after layout and timing closure using the Azuro PowerCentric solution on an ARC Video subsystem core in a 130nm process.

Results were compared against an industry standard EDA flow which included clock gating and clock tree insertion.

"ARC continuously strives to offer best-in-class configurable solutions that fit the stringent needs of customers designing SoCs for power sensitive applications", said Peter Hutton, Senior Vice President of Engineering at ARC International.

"By leveraging Azuro's PowerCentric low power methodology, licensees can further reduce power consumption of ARC's configurable subsystems and processors by more than 20% without impacting processor footprint".

Azuro's PowerCentric uniquely combines clock gating and clock buffering into one unified low power clock implementation solution which completely replaces clock tree synthesis in existing industry design flows.

A demonstration of the technology on an ARC Video Subsystem will be available to qualified companies at the 2006 Design Automation Conference (DAC) in San Francisco.

Interested parties should contact Azuro for more information.

Ashutosh Mauskar, Vice President of Product Marketing for Azuro, said: "By incorporating Azuro's PowerCentric into design flows for ARC's products, our mutual customers are able to deploy extremely power efficient silicon".

"We are happy to be a low power solution for ARC licensees and look forward to future collaborations with the leader in configurability".

Azuro's PowerCentric solution for ARC's configurable subsystems and processor families is available now from Azuro.

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