Product category:
Design and Development Software
News Release from: Azuro | Subject: PowerCentric
Edited by the Electronicstalk Editorial
Team on 01 June 2007
Clock tree synthesis passes nanometre
GPU test
Successful evaluation demonstrates PowerCentric's ability to reduce power and also meet complex variability-driven clock tree implementation requirements.
Nvidia Corporation has entered into a multi-year agreement to purchase Azuro's PowerCentric Nvidia selected PowerCentric after a successful evaluation that demonstrated PowerCentric's ability to reduce power and also meet complex variability-driven clock tree implementation requirements
This article was originally published on Electronicstalk on 17 May 2005 at 8.00am (UK)
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PowerCentric version 3 extends its 15-25% power reduction capabilities to support advanced variability-aware design flows at 65nm and below.
"For Nvidia, we must deliver unmatched features and performance in our graphics, multi-media communication processors and application processors while meeting tight power budgets, performance and area constraints".
"Consequently, our designs contain extremely complex clock trees with multiple branches at the block level that also needs to be balanced for min/max corners", says David Dumoulin, Director of Engineering at Nvidia.
"PowerCentric gives us the ability to implement superior clock trees inside our existing physical framework of EDA tools".
Azuro's PowerCentric is a clock tree synthesis and optimisation solution that brings together unique algorithms for clock tree buffering, gate-level clock gate logic synthesis, and statistical average-case dynamic power analysis, to deliver a completely unified clock implementation solution for advanced nanometre designs.
PowerCentric delivers 15-25% power savings above and beyond traditional EDA flows and also supports concurrent multi-corner clock tree balancing and timing optimisation.
"Designers spend a lot of time getting their clock implementation right, especially within challenging nanometre environments that demand low power, high speed, and high yields all at the same time", says Ashutosh Mauskar, Vice President of Product Marketing for Azuro.
"PowerCentric implements clock gating and clock buffering entirely within one unified step, operating at the placed-gates level in the design flow".
"This enables PowerCentric to explore a larger global solution space of clock gating topologies and make better power-timing-variability tradeoffs than other industry solutions".
"We are very excited to be working with Nvidia at the cutting edge of nanometre ASIC design".
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