Product category:
Design and Development Software
News Release from: Berkeley Design Automation | Subject: Analog FastSpice
Edited by the Electronicstalk Editorial
Team on 26 March 2008
Circuit simulator speeds RF front end
design
Analog FastSpice enables researchers to verify a complete 10GHz full-circuit PLL synthesiser for a wideband satellite TV tuner at the transistor-level with true Spice accuracy.
Berkeley Design Automation has revealed that its Analog FastSpice circuit simulator has delivered an industry first full-circuit PLL synthesiser performance simulation with true Spice accuracy The application was a wideband RFCMOS satellite TV tuner under development at the Berkeley Wireless Research Centre at the University of California Berkeley
This article was originally published on Electronicstalk on 25 Jul 2006 at 8.00am (UK)
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"We are doing pioneering work in the integration of the complete RF front end of a wideband satellite TV receiver (LNA, mixer, frequency synthesiser) in CMOS technology", says Ali Niknejad, Associate Professor of Electrical Engineering and Computer Sciences at UC Berkeley, and Codirector of the Berkeley Wireless Research Centre.
"This integrated RFCMOS approach will dramatically reduce the costs for such receivers while enabling multistandard, multinetwork operation".
"With Analog FastSpice, we were able to verify the complete 10GHz full-circuit PLL synthesiser for this wideband satellite TV tuner at the transistor-level with true Spice accuracy which was impossible with any other simulator".
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Beceem's design teams can now complete full WiMAX transceiver circuit verification as well as verify complex blocks 5-10x faster.
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Analog FastSpice enables SiPort's designers to verify their digital multimedia broadcast receiver designs in a fraction of the time required by traditional Spice tools.
Berkeley Design Automation tools include Analog FastSpice circuit simulation, RF FastSpice periodic analyser, and PLL Noise analyser.
The company guarantees identical waveforms to the leading "golden" Spice simulators down to noise floor (typically 0.1% or less) while delivering 5-10x higher performance and 5-10x higher capacity.
It achieves this by using advanced algorithms and numerical analysis techniques to rapidly solve the full-circuit matrix and the original device equations without any shortcuts that could compromise accuracy.
Design teams from top-10 semiconductor companies to leading startups use Berkeley Design Automation tools to solve big analogue/RF verification problems.
Typical applications include characterising complex blocks (eg PLLs, ADCs, DC/DC convertors, PHYs, Tx/Rx chains) and running performance simulation of full circuits (e.g, wireless transceivers, wireline transceivers, high-speed I/O macros, memories, microcontrollers, data convertors and power convertors).
"We are very pleased with our co-operation with the Berkeley Wireless Research centre", says Ravi Subramanian, President and CEO of Berkeley Design Automation.
"The centre's on-going research on highly integrated wideband RFCMOS solutions with the lowest possible energy consumption and advanced circuit architecture innovations pushes verification tools to the limit".
"We are very proud that our Precision Circuit Analysis technology is an essential component of their success in developing breakthrough RFCMOS architectures for next-generation wireless systems".
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