Closed-loop noise analysis of PLLs

Berkeley Design Automation has announced what it claims as the industry's first closed-loop noise analysis of fractional-N phase-locked loops (PLLs) at the transistor level.

Combining transient noise and periodic noise analysis in the company's Noise Analysis Option device noise analyser, designers can now optimise and characterize all fractional-N and integer-N PLLs for phase noise and jitter prior to silicon fabrication.

The Noise Analysis Option is an option to the company's Analog FastSPICE circuit simulator, which the company claims delivers true SPICE accurate results five to 10 times faster on five to 10 times larger circuits than any alternative.

Fractional-N PLLs are used across a wide variety of applications for their superior resolution and performance.

Until now, however, it has been impossible to accurately analyse their closed-loop phase noise and jitter at the transistor-level, including subtle time-varying device noise effects such as flicker noise and spurs.

Instead, design teams have had to rely on behavioural modeling approximations and costly test chips.

Berkeley Design Automation tools include Analog FastSPICE circuit simulation, Noise Analysis Option device noise analyser, RF FastSPICE periodic analyser, and PLL Noise Analyzer.

The company guarantees identical waveforms to the leading "golden" SPICE simulators down to noise floor (typically 0.1 per cent or less) while delivering higher performance and higher capacity.

It achieves this by using advanced algorithms and numerical analysis techniques to rapidly solve the full-circuit matrix and the original device equations without any shortcuts that could compromise accuracy.

Typical applications include complex-block characterization (for example, PLLs, ADCs, DC/DC converters, PHYs, Tx/Rx chains) and full-circuit performance simulation (for example, wireless transceivers, wireline transceivers, high-speed I/O macros, memories, microcontrollers, data converters, and power converters).

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