Product category:
Design and Development Software
News Release from: BindKey Technologies | Subject: RapiDesignClean
Edited by the Electronicstalk Editorial
Team on 15 April 2003
Design checker runs down to 90nm
RapiDesignClean is the first design for manufacturing product of its kind and is now the first to support manufacturing design rules at 90nm and below.
BindKey Technologies has redeveloped its RapiDesignClean rules-driven layout tool for nanometre IC design RapiDesignClean is the first design for manufacturing product of its kind and now is the first to support manufacturing design rules at 90nm and below
This article was originally published on Electronicstalk on 29 Sep 2003 at 8.00am (UK)
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Used today by leading integrated device manufacturers and fabless semiconductor companies, RapiDesignClean shortens a design team's time to tapeout by enabling layout engineers to produce design-rule-clean layouts fast and with fewer iterations.
"We have completed a major redevelopment of RapiDesignClean to address the step change in requirements at 90nm and below", said Jim Jordan, BindKey's Vice President of Marketing and Business Development.
"With nanometre design, layout engineers are facing an explosion in the number of design rules and design complexity, straining their ability to quickly produce layouts.
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RapiDesignClean enables design teams to easily incorporate and implement manufacturability during the design process".
As chip feature sizes shrink from 130 to 90nm and below, layout engineers face the impossible task of memorising 1000 design rules or more.
Using RapiDesignClean, they don't have to.
RapiDesignClean is the first tool of its kind to provide full support for the most advanced technologies (90nm and below) in real time.
Unlike tools that only check for rule violations after the layout is finished, RapiDesignClean shows layout engineers where to place structures without creating violations - in real time, during the layout process.
RapiDesignClean offers exceptional performance.
Tool speed is crucial because for each edit the layout designer makes RapiDesignClean applies hundreds of rules, and the numbers keep growing with each new generation of technology node.
RapiDesignClean runs with virtually no delay, providing visual feedback of applicable rules at each edit in a fraction of a second.
RapiDesignClean's automation of manual tasks and high performance improve designer productivity, while assuring design rule compliance.
Based on patent-pending technology, the product displays rules as easy-to-read visible "hints" on the layout editor screen.
In addition, it immediately notifies the layout engineer if violations occur, and its "enforce" mode can speed layout and prevent design rule violations by automatically snapping structures back to minimum distance.
From start to finish of a layout, RapiDesignClean applies geometric rules for each individual edit.
And it handles rules that involve complex operations on a combination of layers.
RapiDesignClean today works in tandem with the Cadence Virtuoso layout editor and industry-standard design rule checking signoff tools.
RapiDesignClean imports the design rules directly from the layout editor and from industry-standard design rule tool formats.
It supports design rules for all process technologies including 90nm and below, both analogue and digital, bipolar or CMOS.
"RapiDesignClean is a low-risk, high-reward product", said Jordan.
"It can be implemented at any time during the design process, even when a design group is nearing tapeout and having difficulties.
It integrates with existing tools and doesn't require a change in a customer's design flow or methodology.
It simply automates the process of producing layouts that are free of design rule violations".
RapiDesignClean is available immediately and with pricing starting at $15,000.
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