Product category:
Design and Development Software
News Release from: BindKey Technologies
Edited by the Electronicstalk Editorial
Team on 15 December 2003
Tower adds rules-driven layout solution
Tower Semiconductor has selected BindKey's RapiDesignClean rules-driven layout solution to be part of its standard IC design methodology.
Tower Semiconductor has selected BindKey's RapiDesignClean rules-driven layout solution to be part of its standard IC design methodology RapiDesignClean is the industry's first rules-driven layout solution for custom design of nanometre ICs
This article was originally published on Electronicstalk on 15 Apr 2003 at 8.00am (UK)
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Its highly automated capabilities reduce a design team's time to tapeout by enabling layout engineers to produce design-rule-clean layouts faster and with fewer iterations.
Tower Semiconductor evaluated and selected RapiDesignClean to support its accelerating demand for engineering resources due to the growing number and complexity of the company's design rules.
"On its own, RapiDesignClean has increased layout productivity by more than 20%", said Sergio Kusevitzky, Vice President of IP and Design Services for Tower Semiconductor.
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"Our engineers can quickly acquire high proficiency in new processes because RapiDesignClean significantly reduces the need to memorise complex rule sets.
This provides flexibility in moving engineers between projects, thus optimising the company's resources.
Moreover, we are able to complete designs in a single iteration as RapiDesignClean is applying the same design rules as our signoff DRC tool".
"BindKey is pleased to have this opportunity to contribute to Tower's engineering success", said Jeff Menkes, Vice President, Worldwide Sales for BindKey.
"They understand the productivity advantages of RapiDesignClean and see the increasing need for rules-driven layout with each new generation of process technology".
In the age of nanotechnologies, as chip feature sizes keep shrinking, layout engineers face the impossible task of memorising 1000 design rules or more.
Using RapiDesignClean, they don't have to.
RapiDesignClean is the first tool of its kind to provide full support for the most advanced technologies (90nm and below) in real time.
Unlike tools that only check for rule violations after the layout is finished, RapiDesignClean shows layout engineers where to place structures without creating violations - in real time, during the layout process.
RapiDesignClean offers exceptional performance.
The tool's ability to deliver near-instantaneous response is crucial because for each edit the layout engineer makes RapiDesignClean applies hundreds of rules.
RapiDesignClean runs with virtually no delay, providing visual feedback of applicable rules at each edit session in a fraction of a second.
RapiDesignClean works in tandem with the industry-leading layout editors and DRC signoff tools.
RapiDesignClean imports the design rules directly from the layout editor and from industry-standard DRC formats.
It supports design rules for all process technologies, including 90nm and below, both analogue and digital, bipolar and CMOS.
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