Latest news on Electronicstalk categorised by supplier
Cadence Design Systems
Address:
Bagshot Road
Bracknell
RG12 0PH
UK
Telephone: (UK) +44 1344 360 333
http://www.cadence.com
Our RSS feed for news from Cadence Design Systems
Request to receive our free email newsletter each week
Listing of all 347 news releases from Cadence Design Systems:
IC design offering eases 65nm processes
The Cadence Virtuoso custom design platform offers speedier simulation tools for accurate and efficient verification of complex designs.
News from Cadence Design Systems (30 April 2008)
Circuit simulator receives upgrade
The Cadence Virtuoso Spectre circuit simulator eases the verification of phase-locked loops, analogue-to-digital convertors, transceivers, clock data recovery circuits and power supply circuits.
News from Cadence Design Systems (30 April 2008)
RF design software is qualified at 65nm
Newly qualified technologies deliver tested and proven inductance, substrate extraction and passive component design.
News from Cadence Design Systems (15 April 2008)
University leads in design verification training
Dr Kerstin Eder has been invited to present her work at the Cadence Academic Network Symposium during CDNLive, the Cadence annual user conference
News from Cadence Design Systems ( 8 April 2008)
Software smoothes late design changes
Encounter Conformal ECO Designer helps users evaluate the feasibility of engineering change orders and enables them to implement functional changes to the design very late in the design cycle
News from Cadence Design Systems (26 March 2008)
Cadence acquires Chip Estimate
Chip Estimate customers will benefit significantly from the synergies and opportunities created by the combination of the companies.
News from Cadence Design Systems (13 March 2008)
Common format keeps power in mind
User application article Accent has successfully taped out a low-power RFID application design using the Common Power Format based Cadence Low-Power Solution.
News from Cadence Design Systems (22 February 2008)
Open Verification Methodology is enhanced
Distributed under the standard open-source Apache 2.0 licence, the OVM source code, usage examples and documentation may be downloaded free of charge from OVM World.
News from Cadence Design Systems (15 February 2008)
Verification system aids multimedia development
User application article Incisive Enterprise Manager users can better automate the deployment of their testing, measure simulation runs, analyse failures and coverage data from several sources
News from Cadence Design Systems ( 7 February 2008)
Simulator answers reliability requirements
User application article Toshiba is using the Virtuoso UltraSim Full-Chip Simulator for quantitative simulation methodology for reliability analysis at 65nm and below
News from Cadence Design Systems (24 January 2008)
Reference flow incorporates power reduction system
User application article The Pride V1.5 flow incorporates the CPF-based Cadence low-power design solution to provide an automated and holistic low-power design flow from RTL design through GDS II tape-out.
News from Cadence Design Systems (23 January 2008)
Design technology to give BMW a racing edge
BMW Motorsport and the BMW Sauber F1 Team will deploy technology from Cadence to develop the next generation of leading-edge F1 racing cars.
News from Cadence Design Systems (15 January 2008)
Programme cuts time and risk for start-ups
The Cadence Start-up Accelerator programme will enable Analogies to focus on developing its high-speed PHY IP cores.
News from Cadence Design Systems (14 January 2008)
Open-source software standardises verification
The OVM is the first open language-interoperable SystemVerilog verification methodology in the industry.
News from Cadence Design Systems (11 January 2008)
Reference methodologies speed ARM design
Methodologies for two ARM processors provide enhanced design solutions to mutual customers designing multicore, low-power devices.
News from Cadence Design Systems ( 7 December 2007)
Verification line handles complex chip designs
New offerings in the Incisive Enterprise verification family enable users to handle designs containing hundreds of millions of logic gates.
News from Cadence Design Systems ( 4 December 2007)
Design kits target UMC 65nm process
Virtuoso technology helps accelerate silicon-accurate design of analogue, mixed-signal and RF devices.
News from Cadence Design Systems ( 4 December 2007)
Design services target Russian IC hub
New Russian office in Zelenograd will serve as a centre of excellence for Cadence virtual CAD services.
News from Cadence Design Systems (29 November 2007)
Verification plan speeds overall development
User application article Micronas has selected the Cadence Incisive Plan-to-Closure Methodology and Incisive Enterprise Manager for verification planning.
News from Cadence Design Systems (29 November 2007)
Software eases passive component design
The Virtuoso Passive Component Designer helps designers automatically generate the optimum inductive device for their specific application and process technology.
News from Cadence Design Systems (13 November 2007)
NXP standardises on EDA portfolio
Multicore design optimises ARM performance
Statistics prevent catastrophic silicon failures
Verification kit eases design process
Design company announces new acquisition
Emulator accelerates IC verification
Mixed-signal verification increases coverage
Pattern-synthesis technology acquired
Logic designers get physical with floorplan data
Timing system is integral part of tapeout success
Design platform produces first-time-right silicon
Timing constraint signoff tool passes the test
Design platform enable DDR integration at 65nm
Methodology combines design with verification
Software takes holistic view of PCB design
Single simulator covers all IC technologies
Kit cuts the cost of low-power IC design
Expanded alliance assists IC verification
Design software cuts 65nm TV chip time to market
Early verification boosts IC design productivity
Portable systems stay cool thanks to VoltageStorm
User conferences kick off in Munich
65nm reference flow targets Common Platform
Router adds intelligence to automation
Tool detects issues in design constraints
Design flow adds assertion-based formal analysis
Verification and custom businesses lead growth
Freescale takes kit route to analogue improvement
Power saving design cuts wireless silicon by 30%
Mobile audio chip cuts power and boots first time
Software preserves low-power design intent
Router improves design and manufacturability
Compiler improves timing on large ASIC blocks
Verification reveals more bugs for Ubicom
Wipro selects Cadence for VLSI and system design
Custom design platform adds 90nm RF process
Common power format ahead of schedule
High performance enterprise level verification
Predictable software, hardware and system quality
IBM signs up for 65nm ASIC support
Wireless SoC reference flow bears fruit
IP providers join the programme
Alliance moves towards CPF standardisation
Advanced LSI ICs are designed for testing
Reference methodology aids ARM-based design
Test software improves 90nm delay defect coverage
Emulator accelerates router ASIC proving
Teamwork software unifies concurrent design
Design flow overcomes lithographic limitations
Amkor adopts system-in-package design
Emulation system runs extremely quickly
Platform promises faster route to custom SoCs
System shows timing, signal integrity and power
Fujitsu signs up for timing analysis
Realtek finds critical bugs in power connections
Universal verification components speed closure
Kit formalises analogue methodologies
Cadence reports Q2 revenue up 12%
Automated Design and Implementation Flow
Design and system interconnect go with the flow
Diagnostics technology lead extended
Duesener to direct EMEA market
Architecture cuts handset chipset down to size
Next-generation IC router thinks outside the grid
Software specialises in system-in-package design
Kit verifies the truth about ARM designs
Timing-aware test generation cuts design delays
Flow unites modelling with verification
Initiative unites leaders in low-power design
Software supports 65nm process introduction
Novel approach boosts verification productivity
Specification-driven design works for Zarlink
Reference flow speeds mixed-signal design
Speedy synthesis shrinks ASICs and cuts time
Verification server keeps up with Sun's fast SPARC
IEEE recognises SystemVerilog development work
Collaboration helps create Russian masters
Reference flow optimises 90nm SoC designs
Power-management methodology is enhanced
SoC platform enables a first for set top boxes
Suite makes IC designs more manufacturable
Award recognises new approach to IC design
Simulator speeds to FastSpice results
Cadence maintains steady progress
Software optimises IC designs in 3D
65nm design flow maximises platform benefits
Software set to inspire Russian innovation
IC design software runs under Solaris 10
Testbench automation upgrades verification
Kit addresses key challenges in wireless design
Design platform keeps 65nm processor on schedule
Verification package turns to low-power design
Synthesis package promises optimal QoS
IC design platform adds yield analysis
DVD/CD SoC uses Encounter Test Architect
Kawasaki Micro maximizes delay test coverage
Cadence forms initiative with STARC
Encounter Test family validated on Agilent's 93000
Freescale signs for EDA package
Language progresses towards standardisation
Emulator meets specific needs for Hitachi
Verification moves to the enterprise level
Functional verification takes tailored approach
Teams turn to SystemVerilog-based verification
Cadence commits to e standardisation
Design flow to target complex RF devices
Platform enables early array signoff
Design flow supports latest ARM processor
Comit gains greater access to Cadence technology
Design platform eases migration from 90 to 65nm
Help at hand for PowerPC-based SoC design
Kit focuses on analogue and mixed signal design
Verification system optimised for rapid turnaround
Digital design platform comes in three levels
ARM kits shorten time to productivity
Interconnect design platform enhanced
Quality of silicon is key to ARM-based SoCs
Platform accelerates structured ASIC to silicon
Compiler helps cut consumer IC down to size
Custom ICs drive Cadence growth
Personal PCB design tools move up-market
Fabless startup enlists wireless design expertise
PCB design software is made for teamwork
Compiler synthesis proves popular in Japan
RTL compiler speeds LCD controller to tapeout
Fister takes the reins of power
Compiler speeds image processor to tape-out
Compiler helps cut nanometre designs down to size
Verification strategy mirrors enterprise software
Emulator system speeds telecomms chips to market
Graphics processor shows off X Architecture
IC design platform runs on 64bit Linux systems
Reusable IP accelerates Oki's analogue design
TSMC integrates nanometre design platforms
Reference flow set to boost 90nm SoC productivity
Alliance addresses SI issues at the IP level
RTL compiler delivers production-cost savings
Formal verification comes to the desktop
Endpoint controller certified for PCI Express
Verisity becomes Cadence Verification Division
Symbol set donation to encourage standardisation
Wipro signs up for continued support
PCB CAD package adds signal integrity analysis
Low-power enhancements find favour
Software offers superior internal test structures
Partitioning speeds high-density PCB design
GUC encounters tape-out success
Library views improve signal-integrity analysis
Community aims for closer dialogue
S3 encounters multiple designs at 90nm
Emulation system speeds DTV chip verification
Donation to enhance SystemVerilog usability
Rising gets RF chip right first time
Physical synthesis software scoops DesignCon award
Compiler helps Sanyo reduce power consumption
Fujitsu encounters first-pass success 66 times
Design flow addresses to wireless challenges
Software keeps track of design constraints
Compiler cuts SoC power and area for Oki
Platform accelerates supercomputer chipset
RTL-to-netlist synthesis speeds SoCs to market
Community aims to accelerate PowerPC SoCs
Fabless design house speeds to nanometre IC
Improved verification boosts tapeout confidence
Cell-based extraction qualified at Chartered
Toshiba encounters first time silicon success
Emulator tackles complex SoC verification
More options for entry-level PCB design
Cadence reports solid third quarter
Novel tool promises to boost nanometre yields
Effective current source model gains popularity
Platform gains assertion-based verification
RTL compiler is a qualified SoC success
Renesas aims to cut mask-making times and costs
Cadence helps with Czech EDA lab upgrade
Fujitsu maximises first silicon success
Design platform aids chipset implementation
Reference flow looks beyond 130nm
Stretch shrinks time to market
Emulation system verifies leading-edge graphics
System speeds graphics processor to market
Simulator verifies world's fastest ADC design
EDA deal helps Fujitsu towards IDM business model
Design platform speeds visual processor to market
Platform boosts PCB designer productivity
Emulator offers accelerated SoC verification
New flow speeds 62-million-transistor to tape-out
Enhanced platform accelerates custom IC design
Simulator tackles multigigahertz design
Workbench brings PLM to electronics design
Virtual prototyping and synthesis come together
Pair resolve to bridge software gap
Tools work together to verify system level design
Platform adds support for Virage Logic libraries
Russian R and D centre is a first for Cadence
Online parts database speeds CAD capture
Reference flow supports 90nm process
Platform simplifies Linedancer geometry shrink
Timing delay tester tackles nanometre designs
Router rips through complex IC designs
Design flows for digital nanometre design
Platform reduces verification bottlenecks
Reference flow smooths out mixed-signal SoC design
Compiler qualified for reference flow
Digital IC platform sorts out 8-million-gate SoC
Reference methodology supports speedy new cores
Neolinear acquisition to boost analogue expertise
Baseband tape-out proves merit of 90nm design
Agere accepts Encounter netlists
Implementation platform speeds 90nm DSP to tapeout
Chip integration solution speeds custom design
Support for Korean SoC training
Russian sponsorship shows first fruits
VHDL support speeds silicon synthesis
Barnes returns to European role
Assertion checkers speed effective verification
64bit Intel platforms speed digital IC design
Encounter with 64bit Opteron systems
Incisive decision for eInfochips
Cypress standardises on extractor
Acquisition optimises layout portfolio
Motorola reconfigurable device races to tapeout
Full-chip extractor works on TSMC 90nm process
Signal-integrity analysis for front-end PCB design
Router clocks up a century of tapeouts
Virtual CAD service speeds TV SoC to the show
Linux option is a first for EDA software
Digital baseband speeds to tape-out
SystemVerilog proposed for standardisation
SensorDynamics standardises design methodologies
Package design software verifies signal integrity
Collaboration targets automotive control
Test solutions span design to manufacture
Platform speeds into nanometre design
Tools support latest 90nm process
Design platform maintains nanometre-scale accuracy
More productivity for Windows-based PCB packages
Alliance aims for system-to-silicon solution
Cell-based extractor handles shrinking geometry
Fabless semiconductor company commits to toolset
Full solution for gigabit-speed PCB systems design
Parallel hardware accelerates verification
Cadence to acquire Verplex Systems
CAD services speed camera to tape-out
CAD services smooth product development
PDKs reduce risk and simplify silicon design
Design platform speeds DSL chipsets to market
Delay models accelerate nanometre signoff
Reference flow optimises IBM ASICs
Parallel characterisation speeds Spice
Fast-Spice simulator takes on mixed-signal design
Editor finishes the job in record time
High-speed solution for Asustek motherboards
Compiler speeds chipset to market
Acquisition brings design closer to manufacture
RTL compiler synthesis speeds multicore design
Incisive support for latest FPGAs
Design for test tools take on latest AMD processor
Silicon engineering speeds switch fabric design
Donation accelerates IP assessment
Encounter speeds Wintegra's nanometre designs
Package design suite simplifies die stacking
Environment aids high-speed interface design
Cadence joins automotive development group
ARM deal extended for five years
Signal integrity tool spots damaging glitches
Accelerated verification for nanometre designs
First Encounter for STMicroelectronics
ATI standardises on tools for 90nm and below
Linux-based systems to boost EDA performance
Cadence hits the acquisition trail
Tool suite passes signal integrity test
Distribution for standard-cell libraries
Speed and accuracy boost for parasitic extraction
Source code is step towards tool interoperability
Verification system links with wireless testers
Solid third quarter for Cadence
Cadence and IBM ally to simplify chip design
Cadence selected as prime EDA vendor
Signal-integrity tools tackle nanometre crosstalk
Cadence to dispute Ikos patent claim
Toumaz standardises on Cadence tools and services
d'Eyssautier tackles Europe for Cadence
Kit speeds comms system design chains
Design Foundry business is key to Cadence strategy
Cadence completes Simplex acquisition
Motorola signs up for Cadence parasistic solution
IEEE award recognises corporate innovation
Motorola turns to Cadence for mixed-signal design
Assertion-based verification finds errors early
Enhancements speed integrated design solution
Cadence Chinese operation is first of its kind
Cadence finds its place in the Sun
Ericsson signs up for years of Cadence
Cadence completes Plato acquisition
Cadence to acquire Simplex Solutions
Big changes to PCB design environment
Windows-based suite speeds PCB design
Cadence philosophical about Plato acquisition
ChipPAC standardises on Cadence packages
Cadence and Agilent focus on wireless development
Cadence opens up third-party development
Parasitic extraction technology joins design flow
STMicroelectronics uses Cadence VCC methodology
Design flow speeds multi-million-gate design
Cadence to acquire Silicon Perspective
Siroyan selects Quickturn for emulation solution
