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Design and Development Software
News Release from: Cadence Design Systems | Subject: STMicroelectronics
Edited by the Electronicstalk Editorial
Team on 21 November 2001
STMicroelectronics uses Cadence VCC
methodology
STMicroelectronics has selected the Cadence Virtual Component Co-Design (VCC) for both its automotive and digital consumer platform system-level design methodology and design flow.
STMicroelectronics has selected the Cadence Virtual Component Co-Design (VCC) for both its automotive and digital consumer platform system-level design methodology and design flow STMicroelectronics was one of the original VCC development partners
This article was originally published on Electronicstalk on 21 Oct 2003 at 8.00am (UK)
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STMicroelectronics' Audio and Automotive Division uses VCC for behavioural modelling and architectural exploration in automotive design flows.
For ST's new power train architecture project, VCC addresses those system-level parts of the design flow that significantly influence SoC size and complexity.
This includes behavioural modelling and architecture exploration to enable knowledge transfer with internal and external system customers, and design refinement and export to implementation-level coverification.
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"The VCC environment met our modelling objectives with its unique capabilities for modeling functional and architectural IP at higher levels of abstraction", said Piero Buratti, Design Methodologies Manager for ST's Audio and Automotive Division, Telecommunication and Peripheral/Automotive Groups.
"The new release of VCC is bringing added functionality, which will allow us to build our IP libraries and improve performance evaluation".
Utilising VCC platform models for function and architecture as a virtual prototype lets designers explore at high levels of abstraction and at a very early stage in the design cycle.
According to Maurizio Peri, System to Silicon Design Director for ST's Audio and Automotive Division: "We use VCC to provide our customers with world-class architectures on which they can map their project functionality.
The goal is to select the best available architecture and to refine it based on performance simulation results.
This approach dramatically reduces design cycle time because it eliminates the need for long redesigns due to architecture optimisation after RTL simulations.
In collaboration with one of our major customers we developed a revolutionary dual-processor power train device using VCC and had excellent results".
STMicroelectronics' STBus-based digital consumer platforms specifically address complex SoC designs.
As part of the design flow, ST uses the VCC environment to implement efficient exchange of platform information to its system house customers, thus allowing system-level configuration and analysis.
"Bus performance, simulation speed, and analysis of a SoC design are key issues in the design flow.
VCC allows us to make tradeoffs around these issues at a higher level of abstraction early in the design cycle", said Jean Marc Chateau, Design Director, Consumer and Microcontroller Groups, STMicroelectronics.
Central R and D at STMicroelectronics works with divisional design groups to provide tools and design flows.
"The VCC environment is a key enabler for design chain interaction between system and semiconductor houses at the system-level", said Michele Borgatti, Non-Volatile Memories, System-Level Design Manager in the Central R and D.
"Independent modelling of system architecture, behaviour, and communication - along with the links to implementation - are key features in an efficient, effective design flow".
VCC is the industry's first system-level development environment for hardware/software codesign and IP reuse.
VCC allows designers to confirm critical architectural decisions, such as the hardware and software partitioning of system functionality, early in the design of their first-generation and derivative products.
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