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Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 02 May 2002

Cadence finds its place in the Sun

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Cadence SP and R (synthesis/place-and-route) design technology has been selected by Sun Microsystems for use in the development of some of its largest, most complex ASICs.

Cadence SP and R (synthesis/place-and-route) design technology has been selected by Sun Microsystems for use in the development of some of its largest, most complex ASICs John Brennan, vice president, hardware engineering for the enterprise system products group, at Sun Microsystems said, "We evaluated Cadence SP and R on several complex ASIC designs and found that its integration of synthesis, placement, and global routing gave better results than our previous design flow

The tool provides an appropriate set of industry standard input and output files for handoffs with all of our ASIC vendors for this project.

This physical synthesis tool should provide faster and more predictable timing closure and layout flows".

With Cadence Physically Knowledgeable Synthesis (PKS) and Silicon Ensemble-PKS (SE-PKS) optimisation place-and-route technologies, Sun Microsystems gets a design flow that supports a flat capacity of up to three million gates.

The concurrent optimisation engines in Cadence SP and R technology will allow Sun to optimise a design's logic, placement, and global routing, for improved overall tradeoffs, helping to ensure high quality results.

"We are pleased that Sun Microsystems has chosen Cadence SP and R technology to meet their design needs", said Eric Filseth, vice president of SP and R marketing at Cadence.

"Sun Microsystems' selection of Cadence SP and R reflects the tremendous market momentum for our integrated, front-to-back IC design solution".

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