Motorola signs up for Cadence parasistic solution

Motorola SPS has adopted Assura RCX, the Cadence full-chip 3D device-level parasitic extraction solution, for its analogue and full-custom design flows.

Motorola SPS has adopted Assura RCX, the Cadence full-chip 3D device-level parasitic extraction solution, for its analogue and full-custom design flows.

Motorola's internal mixed-signal design kit is designed to support the processes in the Assura physical verification solution for LVS, DRC and RCX.

Motorola selected Assura RCX because it provides consistently high accuracy for device-level parasitic resistance and capacitance extraction.

Assura RCX also provides the best-in-class integration to the Cadence Analogue Design Environment.

Assura is a tightly integrated part of the Cadence Analogue Design Environment, the industry's de facto standard for analogue and full-custom designs, leading to the highest productivity solution available.

In addition, Cadence Analogue Design Environment users, such as Motorola, experience quick, reliable migration from Diva to Assura.

"Our leading-edge analogue and full-custom designs require accurate device-level parasitic extraction, and most extraction solutions on the market only focus on gate-level, which is insufficient for analogue/mixed-signal designs", said Jim Caravella, manager of Analogue Design Kits at Motorola's SPS.

"So we chose Assura RCX for our device-level extraction.

We found Assura RCX provides consistent high-accuracy results for full-chip, device-level extraction in the 0.13-micron process.

In addition to accuracy, RCX gives us critical functionality to handle the complex analogue devices required by BiCMOS and Power technologies.

More importantly for analogue and custom design is RCX's debugging environment that delivers a graphical environment by which to debug circuit performance problems".

Assura RCX is compatible with Diva design environments.

This endorsement of RCX follows an earlier decision by Motorola to transition its installed base of Diva DRC/LVS (design rule checking/layout-versus-schematic) users to Assura DRC/LVS.

The ease of adoption enabled the migration to Assura within the existing design environment.

"This is another significant endorsement from a global leader in semiconductor solutions who has switched from our competitor's solution to Cadence for a vital piece of its design flow", said Lavi Lev, executive vice president of IC Solutions at Cadence.

"Mixed signal design and advanced interconnect modelling are both key components in 130 and 90nm designs.

Motorola's choice of Cadence further supports our overall effort to be the platform of choice for realisation of complex mixed-signal designs and analogue-digital convergence".

The success of Assura RCX at Motorola builds on similar earlier achievements with other IDMs (integrated device manufacturers), which have validated the speed and performance of RCX as the best in the industry.

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