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News Release from: Cadence Design Systems | Subject: TSMC standard cell and I/O libraries
Edited by the Electronicstalk Editorial
Team on 15 January 2003
Distribution for standard-cell libraries
Cadence Design Systems has become the first full-line distributor of TSMC's internally developed standard-cell and I/O libraries and memories.
Cadence Design Systems has become the first full-line distributor of TSMC's internally developed standard-cell and I/O libraries and memories The two companies are also to collaborate to integrate TSMC's 0.15 and 0.13-micron and Nexsys 90nm standard cell, I/O libraries and memories with the Cadence Encounter design flow, which was qualified to be included as part of the TSMC Reference Flow
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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"This next step in our relationship with TSMC provides our customers with integrated products including the foundation IP, design tools, methodologies, and design services they need to be successful.
Ultimately, we believe this agreement supports the continued growth of the foundry model critical to so many of our customers", she added.
"Our goal in creating this partnership is to provide our customers with an expanded choice of paths to TSMC silicon", said Dr Genda Hu, Vice President of Marketing for TSMC.
"Our collaboration with Cadence helps accomplish this goal by integrating our libraries and memories with leading EDA tools, design methodologies, design services, and special function IP".
Cadence is a long-time member of TSMC's Design Service Alliance.
For designers' silicon success at 0.13-micron and below, their design tools and technologies, methodologies, and libraries must work together to model advanced design rules and silicon performance accurately.
This requires close alignment and co-operation across the design chain between design technology and silicon manufacturing suppliers.
Through existing EDA, IP, and design services partnerships, Cadence and TSMC have invested in collaborative answers to customers' most pressing nanometer design issues, such as signal integrity.
The new library distribution partnership between Cadence and TSMC will enable further integration and development for mutual customers.
For example, TSMC's 0.15 and 0.13-micron and Nexsys 90nm standard cell and I/O libraries include enhanced features for SoC design, such as dual-threshold power tuning, that enable designers to integrate high-speed and low-leakage functionality on the same chip.
Designers will use TSMC libraries, along with library views for Cadence nanometer design technologies, to implement this in the Cadence Encounter methodology.
TSMC's standard cell and I/O libraries for TSMC's 0.15 and 0.13-micron and Nexsys 90nm processes are available from Cadence now.
TSMC's memories will be available from Cadence starting in Q2 2003.
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