Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: CeltIC 4.1
Edited by the Electronicstalk Editorial
Team on 06 March 2003
Signal integrity tool spots damaging
glitches
Cadence Design Systems has made significant enhancements to its CeltIC 4.1 signal integrity solution, a key technology of the Encounter digital IC design platform for nanometre-scale IC designs.
Cadence Design Systems has made significant enhancements to its CeltIC 4.1 signal integrity solution, a key technology of the Cadence Encounter digital IC design platform for nanometre-scale IC designs The enhanced software is up to three times faster than the previous version, includes overshoot-undershoot glitch analysis for sub-130nm silicon technologies, and a built-in timing engine for timing window convergence, and enables an accelerated SI closure flow within the Cadence SoC Encounter RTL-to-GDSII system
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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According to a 2001 Gartner Dataquest study, CeltIC is market leading, with the best SI solution available.
The new 4.1 release extends CeltIC's leadership in advanced nanometre silicon.
"Over the past two years, we have used CeltIC for crosstalk delay and glitch signoff for all our production ASIC designs", said Don Friedberg, Director of Design Methodology for Agere Systems.
"We have successfully taped out all of our 130nm ASICs using CeltIC and have not observed any SI problems in silicon.
This success has enabled our customers to avoid costly schedule delays that can be as much as three to six months when a respin is required.
We believe that the new CeltIC 4.1 with advanced overshoot and undershoot analysis will help us maintain this perfect track record for even our most demanding next-generation communications chips".
The latest CeltIC release includes a key capability for sub-130nm silicon called overshoot-undershoot analysis.
At 90nm and below, very low supply voltages are normally used to control chip power dissipation.
As a result, the transistor layers are manufactured so thin that signals which "glitch" outside the normal range of operation can damage the transistor gate oxide.
This leads to both logic errors and long-term reliability problems on very advanced silicon geometries with low supply voltage.
CeltIC 4.1's glitch analysis automatically detects this overshoot-undershoot noise and provides repair directives to both Cadence and third-party place-and-route systems.
CeltIC 4.1 also features a dramatic improvement in run-time performance, and its own ability to generate compatible timing windows for delay analysis with third-party tools.
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