Product category:
Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial
Team on 24 April 2003
Donation accelerates IP assessment
Agere Systems and Cadence Design Systems have donated the ChartReuse-II IP assessment programme to the VSI Alliance.
To support openness and interoperability for customers, Agere Systems and Cadence Design Systems have donated the ChartReuse-II IP assessment programme to the VSI Alliance (VSIA) ChartReuse-II provides continued enhancements to the OpenMore IP assessment programme previously donated to the Alliance
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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When released in the third quarter of this year, the VSIA Quality Metric will allow designers who adopt this standard to grade IP blocks containing soft and hard IP objectively.
This will then be extended to embedded systems IP containing digital, verification and software IP provided separately or as a system.
Agere Systems, a new member of the VSIA, joins long-standing member Cadence in developing ChartReuse-II to address the growing availability of embedded systems IP and the need to foster IP supplier participation in ensuring consistent, high-quality development of intellectual property to service the marketplace.
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Both companies have joined the VSIA Quality Development Working Group (DWG) to work with the DWG's chairman and members, who have been working diligently toward the release of an updated Quality Assessment metric later this year.
"VSIA is taking the lead in addressing embedded SoCs and has historically addressed the issue of hardware IP quality", said Michael Kaskowitz, VSIA President.
"Many of our members have told us that quality is one of the most important problems they have to address.
The existing work of our Quality DWG, combined with the donation of ChartReuse-II and the volunteer efforts of Agere Systems and Cadence, will result in a common, industry-accepted and readily utilised Quality Metric".
"We've enjoyed our work with Cadence and with the VSIA to create the ChartReuse-II programme", said William Billowitch, IP Design Reuse and Development Manager at Agere Systems.
"The donation of the programme to VSIA will help intellectual property suppliers provide consistently high-quality IP that is easy for semiconductor developers to incorporate into complex designs with low risk".
"We are pleased to work with the VSIA because we share a similar philosophy about the importance of high-quality IP in an emerging embedded-systems marketplace", said Aurangzeb Khan, Cadence Corporate Vice President and General Manager of Cadence Design Foundry.
"Designs at nanometre-scale process nodes will need to integrate an increasingly larger number of predeveloped IP blocks.
So having a good methodology for reusing IP is becoming an increasingly important competitive advantage for semiconductor providers".
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