Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial
Team on 07 May 2003
RTL compiler synthesis speeds multicore
design
Toshiba America Electronic Components has used the Cadence Encounter digital IC design platform with nanometre synthesis technology to deliver a 530MHz synthesisable 64bit dual-issue MIPS core.
Toshiba America Electronic Components (TAEC) has successfully used the Cadence Encounter digital IC design platform with nanometre synthesis technology to deliver a record-breaking 530MHz (typical operating condition) synthesisable 64bit dual-issue MIPS core Cadence RTL compiler synthesis, recently acquired with the purchase of Get2Chip, and the NanoRoute Ultra signal integrity and timing-optimised router worked together seamlessly to produce this complex multi-million-gate 130nm seven-layer metal CPU design
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
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Using RTL compiler synthesis, Toshiba dramatically improved timing performance on its previous generation set-top box design.
It also provided better interconnect structure to ease back-end design closure and meet Toshiba's aggressive performance goals.
For physical implementation Toshiba employed the full complement of NanoRoute Ultra features, including concurrent routing, and timing and signal integrity (SI) optimisation to maximise the performance achieved in RTL synthesis.
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Signal integrity issues, and their impact on delay, were addressed during routing itself for a smooth route to silicon.
"NanoRoute Ultra simply amazed me", said Andy Le, Director of Physical Design and Methodology at TAEC's TX RISC Business Unit.
"It is always a challenge to close on timing during physical implementation, so given the superior results we obtained from RTL compiler synthesis; we feared any potential timing closure issues or performance degradation in the back-end might be magnified.
However, by incorporating NanoRoute Ultra's multi-CPU routing into our design flow, we were able to route the design to completion very quickly.
Not only did timing close right away, but we also maintained the incredible performance boost we achieved from RTL compiler synthesis through final routing".
"NanoRoute Ultra also demonstrated significant value for us with its ability to address signal integrity issues completely on the fly.
NanoRoute's routing-centric wire spacing, layer selection, net ordering and overall topology control SI closure enabled us to produce a totally clean final result that correlated with Cadence CeltIC SI analysis at final signoff.
We could not have achieved these results with any other router".
"It was a pleasure to work with Cadence on integrating NanoRoute Ultra into our design flow", said Shardul Kazi, Vice President of TAEC's TX RISC Business Unit.
"Improving design cycle time of multi-million-gate designs is always our challenge.
The Cadence RTL-to-GDS technology helps us design our high-performance application specific standard products (ASSPs) and custom system-on-chip (SoC) designs with embedded MIPS RISC CPU cores".
"We are very pleased that our Encounter technology with the new RTL compiler synthesis has demonstrated significant benefits to Toshiba's advanced design flow - dramatically better performance results, with significant savings in design cycle time", said Ping Chao, Senior Vice President and General Manager, Chip Implementation at Cadence.
"RTL compiler synthesis and NanoRoute Ultra provide unparalleled technology for the nanometre era and we look forward to continuing to contribute to Toshiba's success".
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