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News Release from: Cadence Design Systems | Subject: Encounter for IBM technology
Edited by the Electronicstalk Editorial
Team on 20 June 2003
Reference flow optimises IBM ASICs
Cadence Design Systems has released a qualified reference flow for IBM technology based on its Encounter platform.
Cadence Design Systems has released a qualified reference flow for IBM technology based on its Encounter platform The reference flow has been validated through a 130 nanometre test design incorporating intellectual property from IBM, Cadence and third-party IP providers
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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The reference flow optimises the silicon design chain, to help enable a low risk path from design to volume production for Cadence and IBM foundry customers.
The flow has been qualified for the Ready for IBM Technology mark establishing it as validated and compatible with IBM Microelectronics products.
"The development of this reference flow is another step in the ongoing collaboration between Cadence and IBM", said Michael Concannon, Vice President of Foundry and Complimentary Products, IBM Microelectronics division.
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"This reference flow will enable our customers to achieve a quicker path to production silicon, with reduced design risk, using the leading edge IBM process technologies".
The reference flow for nanometre designs utilises the Cadence Encounter platform from virtual prototyping through physical implementation.
The platform offers the industry's first complete RTL-to-GDSII hierarchical integrated circuit (IC) implementation solution for nanometre design.
"The availability of the Cadence Encounter reference flow enables customers to take full advantage of IBM's leading-edge chip-making technology through IBM's foundry business", said Charlie Huang, Corporate Vice President of Business Development at Cadence.
"With the combination of superior IBM processes and market-leading Cadence design tools, we have improved productivity, to help our customers achieve the shortest path from design to volume production for nanometre designs".
The Cadence Encounter-based reference flow builds on a long-standing relationship between IBM and Cadence.
In September 2002, IBM and Cadence established a new series of agreements including extending IBM's use of existing tools, and adding new tools to design chips for both internal purposes, as well as for external customers.
In addition, Cadence acquired IP associated with select IBM in-house EDA test tools for incorporation into the Cadence product family.
Finally, in addition to achieving the "Ready for IBM Technology" mark, Cadence has been awarded Advanced Business Partner status within IBM's PartnerWorld for Developers - a worldwide marketing and enablement programme for all business partners across IBM.
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