Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter Version 3.2
Edited by the Electronicstalk Editorial
Team on 29 September 2003
Platform speeds into nanometre design
Version 3.2 of the Cadence Encounter digital IC design platform delivers enhanced timing optimisation, placement and other technology for very large, fast ICs.
Version 3.2 of the Cadence Encounter digital IC design platform delivers enhanced timing optimisation, placement and other technology for very large, fast ICs The result is more rapid design closure and shorter overall development times
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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In addition to improved timing optimisation and placement, Encounter 3.2 includes a new-generation technology that enables design teams to quickly assess the routing feasibility of different chip-floorplan and package-layout combinations, speeding the design of flip-chip and other large designs containing many hundreds of ports or more.
Additional enhancements include ECO routing capability in NanoRoute, NanoRoute technology in virtual prototyping, and improved clock tree algorithms for high-speed designs.
These are key enablers for designer productivity, reducing optimisation cycles in timing- and signal integrity (SI)-critical designs.
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"We are impressed with the recent progress made within Encounter to support concurrent silicon-package design", said Rick Sergi, Technical Manager, IO Floorplanning Group at Agere Systems.
"As partners with Agere in developing these new capabilities, Cadence has been extremely responsive in introducing tools that will facilitate a collaborative approach to design of the silicon-package interface".
Ikanos Communications, developer of broadband access products with a new class of smart silicon solutions, used the Encounter platform to develop its next generation chipset.
"We have a strong Cadence tradition at Ikanos.
We have used Cadence's place and route solution to achieve first pass success on eight chips over the last three years.
Our Design team upgraded to SoC Encounter for the latest generation of chips in 0.13um.
SoC Encounter enabled our hierarchical design implementation including complete design closure", said Anoop Khurana, Vice President of Engineering at Ikanos Communications.
"We were worried about possible signal integrity issues due to complexity of our chip.
SoC Encounter's SI-aware routing coupled with SI analysis decreased the number of SI violations to less than 30 per hierarchical block.
These violations were fixed automatically before final tapeout.
Our team felt that having the same engine for SI checking during design implementation and final signoff was a key advantage to successful design closure.
SoC Encounter helped us produce working silicon, production released in Revision A, in a record time".
Design house Time to Market (TTM) specialises in high-quality, reliable ASIC and FPGA design services, which it provides to growing numbers of the world's top system houses, cutting-edge communication industry suppliers and network startups.
TTM's expert team of designers relies on Cadence's proven Encounter platform to deliver production silicon.
"Our tapeout experience with the Cadence Encounter platform has shown a consistent reduction in the number of timing iterations.
This enables us to meet the schedule for all our high-end ASIC tapeouts", said Venkata Simhadri, TTM's President and CEO.
"We recently taped out a multi-million-gate, 130nm ASIC running at 300MHz.
The Encounter platform helped us achieve timing closure very quickly.
We used the complete SoC Encounter flow for floorplanning, timing closure, place-and-route, and SI analysis.
We also taped out an eight-million-gate, 180nm flip-chip ASIC with the Cadence Encounter platform by developing a flip-chip methodology around the Encounter platform.
TTM is looking forward to more challenging tape-outs using the Encounter platform".
"Encounter 3.2 marks another step forward in our delivery of advanced EDA technology.
We deliberately set out to build a system with best-in-class technology at the key tool nodes, which would apply first and foremost to high-end, large, hierarchical designs, at 130nm and below", said Wei-Jin Dai, Vice President, Chip Implementation at Cadence.
"We are very pleased with the continuing rate of customer adoption and successful tapeouts on aggressive SoC designs".
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