Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Virtuoso
Edited by the Electronicstalk Editorial
Team on 04 March 2004
Chip integration solution speeds custom
design
Cadence Design Systems has optimised its Virtuoso custom design platform with the availability of a new chip integration flow, coupled with the newest release of its Virtuoso Chip Editor.
Cadence Design Systems has optimised its Virtuoso custom design platform with the availability of a new chip integration flow, coupled with the newest release of its Virtuoso Chip Editor By using these solutions together, designers will, for the first time, be able to perform full-scale physical integration across multiple design domains, including analogue, custom digital, RF, memories/arrays and digital standard cells from a full-custom point of view
This article was originally published on Electronicstalk on 26 May 2003 at 8.00am (UK)
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Editor finishes the job in record time
The Virtuoso Chip Editor chip finisher uses the OpenAccess application programming interface and database to directly link the Encounter digital platform with the Cadence custom environment.
Design platform maintains nanometre-scale accuracy
The Virtuoso custom design platform is claimed to be the world's first comprehensive platform for fast, silicon-accurate custom, analogue, RF and mixed-signal design.
This new generation Cadence technology offers up to 10 times performance improvement over existing custom design solutions.
It is also capable of shortening physical design integration from one month to approximately two weeks in a typical advanced mixed-signal design with over 1.5 million transistors.
Cadence's chip integration flow and Virtuoso Chip Editor provide designers an automated physical design integration solution from floorplanning through chip finishing and tape-out, resulting in significant productivity gains and faster time-to-market.
Further reading
Enhanced platform accelerates custom IC design
Improvements to the Virtuoso custom design platform bring significantly greater speed and productivity to analogue, custom and RF design.
Simulator verifies world's fastest ADC design
The Virtuoso UltraSim FastSpice simulator has been successfully deployed by TelASIC Communications to verify the company's TC1410 analogue/digital convertor (ADC).
Design flow addresses to wireless challenges
New software aims to give wireless chip designers and manufacturers better insight into the mixed-signal and radio frequency challenges that significantly impact wireless design.
Building on Cadence's commitment to drive open collaboration for its customers, the new chip integration solution provides a seamless bidirectional integration path to and from the Cadence Encounter digital IC design platform through the OpenAccess database.
"The industry needs flows and tools which address the lack of interoperability that hinders the speed at which complex SoCs have to be produced", said Steve Schulz, President and CEO of the Silicon Integration Initiative (Si2).
"The fact that the new Cadence chip integration flow and Virtuoso Chip Editor are based on OpenAccess offers designers greater flexibility and faster SoC assembly across multiple design environments".
"The chip integration flow is a key component of the Virtuoso platform and it is the first of its kind in the industry enabling semiconductor manufacturers to bring multiple design domains together into a single chip implementation", said Felicia James, Vice President and General Manager of the Cadence Virtuoso custom IC design platform.
"With this advanced custom design flow, customers can resolve the challenges in designing mixed-signal ICs so that first-pass silicon can be achieved much faster and with greater predictability".
The Cadence Virtuoso platform is integrated with the Cadence Encounter platform through OpenAccess, ensuring interoperability between custom and digital design environments.
This versatility enables the right solution to be applied to the right design task.
The chip integration flow also builds upon the OpenAccess database, allowing the full custom designer a clear, seamless integration path into the digital design environment.
In addition, Cadence is releasing an enhanced version of its Virtuoso Chip Editor - version 3.3 - to further increase layout productivity.
Highlights of version 3.3 include immediate visual feedback on design rule violations and advanced connectivity awareness that speeds up chip finishing by alerting the user of accidental opens and shorts.
Virtuoso Chip Editor 3.3 offers more efficient editing of full-chip finishing tasks.
Supported by robust design tools and a "meet-in-the-middle" methodology that combines the speed of top-down design with the silicon accuracy of bottom-up design, Cadence's new chip integration flow embodies the critical elements required to successfully develop mixed-signal custom designs.
This includes the capability to bidirectionally pass data between multiple design domains, floorplanning capability to facilitate top-down and bottom-up design early on, analogue routing capability to facilitate continuous evolution, early and frequent parasitic and analysis capability, and chip finishing capability for large design databases.
The new Cadence chip integration flow and Virtuoso Chip Editor are available immediately on HP, Sun, IBM and Linux platforms.
The detailed, step-by-step flow is based on a distributable 15 million-transistor Ethernet switch and process design kit.
Free workshops about the new flow and Virtuoso Chip Editor will be available in March.
US pricing for a one-year license of the Virtuoso Chip Editor starts at $40,000.
Specific operating system support varies by product.
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