Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter RTL Compiler
Edited by the Electronicstalk Editorial
Team on 26 March 2004
Agere accepts Encounter netlists
Agere Systems now accepts netlists produced by Cadence Encounter RTL Compiler synthesis for implementation in its ASIC design centres.
Agere Systems now accepts netlists produced by Cadence Encounter RTL Compiler synthesis for implementation in its ASIC design centres Used throughout the silicon design chain by intellectual property (IP) vendors, IC, and ASIC designers, Encounter RTL Compiler synthesis works to increase overall chip speed, reduce turnaround time, and help customers achieve the highest quality of silicon (QoS)
This article was originally published on Electronicstalk on 19 Feb 2004 at 8.00am (UK)
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Encounter RTL Compiler synthesis is a key component of the Encounter digital IC design platform and a critical step in the fastest route to superior silicon.
"Agere is committed to providing our customers with access to their choice of the best design technology that will ensure smooth transition from netlist to successful tape-out", said Don Friedberg, Director of Design Methodologies for Agere.
"Agere is pleased to add Encounter RTL Compiler to the list of tools we support".
The new generation technology behind Encounter RTL Compiler delivers global synthesis for timing closure using a unique set of global synthesis algorithms that maximise the performance of challenging designs.
These algorithms identify key leverage regions in the design to optimise.
The result is a superior netlist for routing the design in a shorter period of time.
In some cases runtime can be up to three times faster compared to conventional flows.
This supports Cadence's overall wire centric approach to design with the Encounter platform.
"Getting faster chip speed with smaller die size in less time is valuable to every design team.
The superior RTL Compiler results on our high-density gigabit Ethernet switch, gave us a much shorter timing closure process than we expected", said Shankar Mukherjee, Director of Ethernet Switch Development at Agere.
"Having more margin on this complex multi-million-gate IC before place and route made our ASIC handoff much smoother".
"Agere's use of Encounter RTL Compiler is a testament to our mutual goal of providing customers with design solutions that allow them to achieve outstanding QoS in less time", said Dr Chi-Ping Hsu, Corporate Vice President, Synthesis Solutions, Cadence Design Systems.
"The new generation technology behind Encounter RTL Compiler enables significant timing closure improvements which are so critical to our customers' success".
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