Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: SoC Encounter
Edited by the Electronicstalk Editorial
Team on 15 April 2004
Digital IC platform sorts out
8-million-gate SoC
Toshiba America Electronic Components (TAEC) has successfully implemented an 8-million-gate SoC using the Cadence Encounter digital IC platform.
Toshiba America Electronic Components (TAEC) has successfully implemented an 8-million-gate SoC using the Cadence Encounter digital IC platform The chip, a networking switch, has a maximum clock speed of 300MHz and was designed using the Toshiba 130nm TC280 technology with a flat design methodology
This article was originally published on Electronicstalk on 1 Nov 2004 at 8.00am (UK)
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Toshiba encounters first time silicon success
Toshiba Corp and Toshiba Microelectronics Corp have successfully taped out a 24-million-gate chip using Cadence SoC Encounter.
Design platform keeps 65nm processor on schedule
The Cadence Encounter digital IC design platform has helped PA Semi develop its new 65nm multicore PWRficient processor with a successful test-chip tapeout in March 2005.
Cadence Encounter provides a fast route to quality silicon, particularly for complex, high-performance SoC designs.
With this successful tape out, the Encounter platform has become a fully supported digital IC implementation platform for TAEC.
"We are very pleased with the results we achieved with the Cadence Encounter platform.
We have successfully used the Encounter virtual prototyping and planning capabilities to enhance our SoC design productivity for the past two years.
Encounter has provided us with a fully integrated design flow from prototyping through GDS with excellent performance and turn-around times for big, fast 130-90 nanometre SoC designs", said Shigenori Imazato, Vice President of Engineering Design Centres, TAEC.
"The Encounter technology, augmented by exemplary support by Cadence, allowed us to complete tape out of the SoC entirely within the Encounter platform.
We will continue using the Cadence Encounter platform in production for TAEC designs".
In order to achieve the highest quality of silicon with the simplest design flow, TAEC used the Cadence SoC Encounter physical implementation tool and wires-first methodology.
The SoC Encounter tool's unique high capacity and fast run times allowed the TAEC team to use a flat design methodology for a larger chip than would otherwise not have been possible.
"We are delighted to see Toshiba successfully implementing aggressive nanometer designs using the Cadence Encounter platform", said Wei-Jin Dai, Platform Vice President, Digital IC Implementation, Cadence Design Systems.
"Toshiba is a highly valued customer for Cadence.
This tape out underscores our ongoing commitment to customer success as measured in quality silicon".
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