Product category:
Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial
Team on 16 April 2004
Compiler qualified for reference flow
Taiwan Semiconductor Manufacturing Company is to integrate the Cadence Encounter RTL Compiler into its next-generation reference flow.
Taiwan Semiconductor Manufacturing Company is to integrate the Cadence Encounter RTL Compiler into its next-generation reference flow TSMC's qualification of Cadence's RTL Compiler marks another milestone in the companies' long-standing design chain collaboration
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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The inclusion of RTL Compiler addresses key nanometre performance goals, improves timing closure, reduces device area and lowers power consumption for complex multi-million-gate SoCs.
RTL Compiler effectively uses TSMC's multiple-Vt (voltage threshold) libraries to optimise performance and leakage power in a single-pass optimisation flow.
"We intend to instil designer confidence that high quality silicon is achievable, despite escalating chip complexity", said Genda Hu, Vice President of Corporate Marketing at TSMC.
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"Integrating Cadence's RTL Compiler into our next-generation reference flow should help resolve challenging design issues and leverage TSMC libraries".
"As designers of complex industry leading graphics chips, we require the next-generation synthesis capabilities offered by Cadence's RTL Compiler", said Greg Buchner, Vice President of Engineering at ATI Technologies.
"By using RTL Compiler for some of our designs, we have been able to realise improved timing and reduced chip area along with a shortened design cycle time.
The design methodology advances resulting from close collaboration between our partners TSMC and Cadence are important to our continuing success".
In nanometre design, every aspect of a chip becomes dominated by interconnect-related parameters, design rules, and failure mechanisms.
In order to truly understand the physical properties of a design at 130nm and below, a new, meaningful metric for speed, area, power and test must be applied.
QoS is the new generation metric that incorporates the impact of interconnect on design results "after wires".
Encounter RTL Compiler synthesis uses a unique, patented set of global focus synthesis technologies that offer chip designers the highest QoS in less time and with less effort, while still being backward compatible with the previous generation of synthesis tools that are based on quality of results measurements.
"RTL Compiler has been successfully applied in production by many of the design teams undertaking the industry's most challenging projects and is gaining momentum with leaders such as TSMC", said Dr Chi-Ping Hsu, Corporate Vice President, Synthesis Solutions, Cadence Design Systems.
"RTL Compiler's best-of-breed global synthesis technology is yielding our customers higher performance or smaller area, or both".
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