Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: True-Time
Edited by the Electronicstalk Editorial
Team on 21 May 2004
Timing delay tester tackles nanometre
designs
Cadence Design Systems reckons it has brought timing to the manufacturing floor with True-Time delay test for processes at 130nm and below.
Cadence Design Systems reckons it has brought timing to the manufacturing floor with True-Time delay test for processes at 130nm and below This addition to Cadence Encounter Test helps ensure the highest quality-of-silicon (QoS) by detecting subtle IC defects
This article was originally published on Electronicstalk on 29 Nov 2005 at 8.00am (UK)
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Kawasaki Micro maximizes delay test coverage
Kawasaki Microelectronics has selected Cadence Encounter True-Time technology, the delay test ATPG that uses design timing to automatically generate faster-than-at-speed delay tests.
Timing-aware test generation cuts design delays
Comit Systems has standardised its automatic test pattern generation (ATPG) flow on Cadence Encounter Test.
Artisan Components is one of the first design chain partners to complete True-Time certification of its 90nm standard cell libraries.
True-Time detects subtle delay defects such as resistive opens that can cause catastrophic failures in the end-product application.
With the addition of True-Time, Encounter Test is the first and only tool that uses actual standard delay format (SDF) timing information from the design process to create timing-accurate delay tests.
Further reading
Test software improves 90nm delay defect coverage
Azul Systems has directed its manufacturing test generation development process to Cadence Encounter True-Time Test ATPG solution.
Design flow speeds multi-million-gate design
Advanced Hardware Architectures has designed and taped-out a 10-million-gate forward error correction IC using the 64bit Cadence SP and R design flow.
By tightly controlling the timing of each test using True-Time, Encounter Test automatically maximises the quality and effectiveness of the test for a given test coverage.
"We have worked very closely with Cadence as it developed True-Time", said Garry Hughes, Vice President, ASIC Development and Worldwide Design Centres, IBM Systems and Technology Group.
"With Encounter Test, we have been able to achieve transition fault coverage greater than 90% with automated calculation of tester timings".
"This is in addition to our existing 99% stuck-at fault coverage capability".
"We have seen shipped product quality improve by up to 2x".
"As a result, our goal is to use True-Time for all ASIC devices at 130nm and below".
Encounter Test Design Edition uses True-Time delay test to detect the complex defects that become dominant in nanometre-scale designs.
Encounter Test Manufacturing Edition provides world-class diagnostics for all detectable defects-including those discovered with True-Time.
With a customer proven 80% callout accuracy, Manufacturing Edition accelerates the yield ramp goals of manufacturers.
As is the case with the IBM ASIC libraries, Artisan libraries have been certified for True-Time.
With certified Artisan libraries, designers can be confident that all of the timing information required to generate True-Time delay tests is readily available and fully verified.
"As a leading semiconductor IP provider, Artisan believes that True-Time certified libraries can help designers reach silicon success", said Neal Carney, Vice President of Marketing at Artisan.
"We believe that these libraries, when coupled with Encounter Test, will help provide an advantage to our customers".
"True-Time delay test provides Encounter Test customers the highest quality-of-test available in the industry", said Paul Estrada, General Manager of Encounter Test for Cadence Design Systems.
"We are delighted to continue the track record our development team has of delivering high-value test innovations".
True-Time is available immediately as part of the Encounter Test Design Edition ATPG Plus option.
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