Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial
Team on 04 June 2004
Platform adds support for Virage Logic
libraries
Support is now available for both Virage Logic ASAP Logic structured-ASIC Metal Programmable and Standard Cell Libraries within the industry-leading Cadence Encounter digital IC design platform.
Support is now available for both Virage Logic Area, Speed and Power (ASAP) Logic structured-ASIC Metal Programmable and Standard Cell Libraries within the industry-leading Cadence Encounter digital IC design platform This leverages the production-proven capabilities of SoC Encounter's IC implementation in the structured array, as well as standard cell markets
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
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Further, it enables mutual customers to make tradeoffs between density, cost and performance according to their requirements.
This capability is deployed with SoC Encounter 3.3, in production now.
"Cadence support of Virage Logic's structured-ASIC libraries provides a real advantage to customers", said Lavi Lev, Cadence Executive Vice President and General Manager.
"It expands our industry-leading support in this critical emerging marketplace from traditional ASIC vendors to COT customers, who now can enjoy the benefits of the structured-ASIC approach within the integrated RTL-to-GDSII design environment of SoC-Encounter".
"We are excited to announce mutual support for our ASAP Logic Metal Programmable Cell Libraries within the SoC Encounter platform", said Adam Kablanian, President and Chief Executive Officer of Virage Logic.
"The large installed base of SoC Encounter users now has the flexibility of mixing and matching our metal programmable and standard cell libraries on the same design to achieve maximum savings in overall chip costs".
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