Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial
Team on 14 July 2004
New flow speeds 62-million-transistor to
tape-out
Cadence has provided a complete back-end design flow for one of Motorola's most complex chips, incorporating more than 62 million transistors.
Cadence has provided a complete back-end design flow for one of Motorola's most complex chips, incorporating more than 62 million transistors When Motorola initiated the design of the MRC6011 reconfigurable compute fabric (RCF) device, it ushered in a new era in signal processing with a highly complex and powerful device that delivers 24 (16bit) GMACs of horsepower
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
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The MRC6011 is suited for MIPS-intensive, complex tasks in computationally intensive applications such as baseband processing for 2.5G and 3G basestations, broadband wireless access systems and signal processing for advanced features such as adaptive antenna (AA) and multi-user detection (MUD).
The MRC6011 is also a highly programmable device that offers system-level flexibility and scalability while inducing the competitive cost and power consumption metrics of an ASIC-based approach.
Consisting of six RCF cores, it has an optimised memory subsystem and specialised external interfaces, plus high-speed local buffers and a RISC processor.
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Each core consists of an array of 16 reconfigurable cells (RCs) connected through a flexible and high-bandwidth fabric.
The device, which has a working frequency of 250MHz and over 62 million transistors, complements traditional DSPs in an efficient system-level solution.
Previously, Motorola had used a non-Cadence design flow and so had the operational challenge of migrating the project team to the Encounter platform and design methodology.
Given that the MRC6011 was designed at 130nm geometries, the design team faced the additional technical complexities associated with designing such a large and powerful chip at such a small footprint.
A team from Cadence Design Systems worked to set up a complete back-end flow for working at 130nm and to support the successful physical design of the MRC6011.
In designing what is one of the largest chips, for the TSMC 130nm low voltage overdrive technology with eight-layer copper interconnect, Motorola used a new flow based on the Cadence Encounter platform.
This allowed Motorola to achieve a first silicon tape-out both cost-effectively and within its aggressive project timescale.
The flow developed began with hierarchical floorplanning including "power planning" using First Encounter, which was then used to undertake placement, clock tree, scan chain reordering, timing optimisation, crosstalk repair, filler cell insertion and metal filling.
Timing-driven and signal-integrity-driven routing was accomplished with Cadence's Nanoroute, then crosstalk analysis - both glitch and crosstalk-induced delay - was undertaken using CeltIC.
Finally, Fire and Ice was used for parasitic extraction and First Encounter again for static timing analysis.
The Encounter-based flow and Cadence's design service enabled the project team to achieve tape out at 130nm and the target 250MHz frequency.
The hierarchical design approach was particularly crucial in enabling the finished product to feature more than 62 million transistors.
One of the design team's primary goals was to significantly speed up the migration.
We have an extremely experienced IC design team but needed to transition these skills to a nanometre-scale design methodology.
Using the Encounter platform enabled this to happen, particularly given the signal integrity effects encountered during the design cycle.
Beyond the provision of a complete back-end design flow solution, Motorola highlights the high level of support that the Cadence's services team in France brought to its development group throughout the MRC6011 project.
Cadence demonstrated its prime EDA vendor vision by not only providing tools and services, but also by streamlining the global process and extending it to the foundry step.
The result is one of Motorola's latest innovations in chip design, providing a product to Motorola's market that enables flexibility and low cost of ownership.
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