Product category:
Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial
Team on 04 February 2005
Physical synthesis software scoops
DesignCon award
Cadence First Encounter Global Physical Synthesis technology has won the International Engineering Consortium DesignVision award for ASIC and IC Implementation at DesignCon 2005.
Cadence First Encounter Global Physical Synthesis (GPS) technology has won the International Engineering Consortium (IEC) DesignVision award for ASIC and IC Implementation at DesignCon 2005 First Encounter GPS integrates silicon virtual prototyping and second-generation global physical synthesis technology into a single environment optimised for very large-scale system-on-chip design
This article was originally published on Electronicstalk on 10 Jun 2004 at 8.00am (UK)
Related stories
Virtual prototyping and synthesis come together
First Encounter Global Physical Synthesis (GPS) is a new product that integrates silicon virtual prototyping and second-generation global physical synthesis technology into a single environment.
Design flow speeds multi-million-gate design
Advanced Hardware Architectures has designed and taped-out a 10-million-gate forward error correction IC using the 64bit Cadence SP and R design flow.
STMicroelectronics uses Cadence VCC methodology
STMicroelectronics has selected the Cadence Virtual Component Co-Design (VCC) for both its automotive and digital consumer platform system-level design methodology and design flow.
Building on the Cadence Encounter digital IC design platform's recognised leadership in the market, First Encounter GPS leverages Encounter RTL Compiler's global-focused synthesis methods to close timing quickly even on very large circuit blocks.
This in turn supports the rapid design and assembly of densely integrated ICs common in high end graphics, networking and processor applications.
First Encounter GPS supports RTL-to-placed gates and netlist-to-placed gates design flows.
"We are very proud that the International Engineering Consortium selected us", said Wei-Jin Dai, Platform Vice President, Digital IC Implementation at Cadence.
"This is further validation that First Encounter GPS's physical synthesis is living up to the reputation it began building last year".
"The growing number of high end tapeouts and now this award reflect our commitment to helping Cadence customers put very complex and differentiated electronics into silicon, ahead of their competitors".
With over 100 90nm designs either taped out or underway, and multiple 65nm projects in progress, First Encounter GPS provides a production-proven path to high end silicon.
• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
