Product category:
Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial
Team on 30 May 2005
Reference flow set to boost 90nm SoC
productivity
Cadence Design Systems has outlined the next steps of its ongoing collaboration with IBM and Chartered Semiconductor Manufacturing to provide advanced solutions to enable SoC designs at 90nm.
Cadence Design Systems has outlined the next steps of its ongoing collaboration with IBM and Chartered Semiconductor Manufacturing to provide advanced solutions to enable system-on-chip (SoC) designs at 90nm The three companies are jointly developing a low-power design reference flow for the IBM-Chartered 90nm common process platform
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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"IBM and Chartered continue to drive a common platform for 90-nanometre designs", said Steve Longoria, Vice President, Semiconductor Technology Platform for IBM.
"This low-power reference flow is developed in collaboration with Cadence to tackle the complex design challenges of 90nm and below".
"The combination of the IBM-Chartered 90nm process technologies and Cadence's low-power design methodology will help address the challenges that designers are facing in doing power-efficient IC designs".
"Power management, compressed market windows and the high cost of silicon re-spins are requiring a virtual re-aggregation of the design chain", said Jan Willis, Senior Vice President, Industry Alliances at Cadence.
"Extending our collaboration with IBM and Chartered in support of their common platform exemplifies how Cadence is working across the design chain to provide solutions to accelerate 90-nanometre design for the mainstream".
"We continue to build on the work we've done with Cadence to develop solutions accelerating our customers' path to silicon while increasing their design productivity", said Kevin Meyer, Vice President of Worldwide Marketing at Chartered.
"Cadence is providing advanced low-power technologies for 90-nanometre design that will enable customers to maximise the benefits of technology and choice offered by the common platform".
This reference flow, developed by Cadence Engineering Services, will address critical low-power design concerns, from prototyping through power, timing and area optimisation.
The Cadence Encounter platform enables timing-aware leakage power and dynamic power optimisation, using power techniques such as multi-supply voltages, voltage scaling, clock gating and dual voltage optimisation.
This optimisation helps designers improve timing closure and reduce device area, while lowering power consumption without compromising performance.
"We have been collaborating with Cadence to provide library views based on their ECSM format to more effectively optimise low-power chip designs", said Neal Carney, Vice President of Marketing, ARM.
"As part of this reference flow, the Artisan low-power platform will incorporate the architectures, circuit designs and low-power features that enable designers to successfully use Cadence's unique chip-level power management techniques to create power-efficient SoCs".
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